Shimeng Yu is an associate professor of electrical and computer engineering at the Georgia Institute of Technology in Atlanta, Georgia. He received the B.S. degree in microelectronics from Peking University, Beijing, China in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, California, in 2011 and in 2013, respectively. From 2013 to 2018, he was an assistant professor of electrical and computer engineering at Arizona State University, Tempe, Arizona. He joined the ECE faculty at Georgia Tech in fall 2018.
R. Liu, X. Peng, X. Sun, W.-S. Khwa, X. Si, J.-J. Chen, J.-F. Li, M.-F. Chang, S. Yu, “Parallelizing SRAM arrays with customized bit-cell for binary neural networks,” ACM/IEEE Design Automation Conference (DAC) 2018.
X. Sun, S. Yin, X. Peng, R. Liu, J.-S. Seo, S. Yu, “XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks,” IEEE/ACM Design, Automation & Test in Europe (DATE) 2018.
S. Yu, “Neuro-inspired computing with emerging non-volatile memory,” Proc. IEEE, vol. 106, no. 2, pp. 260-285, 2018.
L. Gao, P.-Y. Chen, S. Yu, “NbOx based oscillation neuron for neuromorphic computing,” Appl. Phys. Lett., 111, 103503, 2017.
P.-Y. Chen, X. Peng, S. Yu, “NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures,” IEEE International Electron Devices Meeting (IEDM) 2017.
S. Yu, P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid State Circuits Magazine, vol. 8, no. 2, pp. 43-56, 2016, invited review.
L. Gao, P.-Y. Chen, R. Liu, S. Yu, “Physical unclonable function exploiting sneak paths in resistive cross-point array,” IEEE Trans. Electron Devices, vol. 63, no. 8, pp. 3109-3115, 2016.
S. Yu, Z. Li, P.-Y. Chen, H. Wu, B. Gao, D. Wang, W. Wu, H. Qian, “Binary neural network with 16 Mb RRAM macro chip for classification and online training,” IEEE International Electron Devices Meeting (IEDM), 2016.
S. Yu, P.-Y. Chen, Y. Cao, L. Xia, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect,” IEEE International Electron Devices Meeting (IEDM) 2015, invited.
P.-Y. Chen, S. Yu, “Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4022-4028, 2015.
R. Liu, D. Mahalanabis, H. J. Barnaby, S. Yu, “Investigation of single-bit and multiple-bit upsets in oxide RRAM-based 1T1R and crossbar memory arrays,” IEEE Trans. Nucl. Sci. , vol. 62, no. 5, pp. 2294-2301, 2015.
R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Experimental characterization of physical unclonable function based on 1kb resistive random access memory arrays,” IEEE Electron Device Lett., vol. 36, no. 12, pp. 1380-1383, 2015.