Visvesh S. Sathe received the B.Tech. degree from the Indian Institute of Technology, Bombay and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor. He joined Georgia Tech. in 2022, where his group, the Processing Systems Lab (PSyLab) conducts research on a broad range of problems in energy-efficient computing and implantable electronics.
Prior to joining Tech, Visvesh was Associate Professor at the University of Washington (2013-2022), and a Member of Technical Staff in the Low-Power Advanced Development Group at AMD (2007-2013). At AMD, his work involved inventing and translating energy-efficient circuit technologies into next-generation microprocessors. Visvesh led the research and development effort which resulted in the first resonant clocked production processor. While at AMD, he co-developed the adaptive clocking architecture for supply droop mitigation which has been subsequently transferred into volume production. His current research interests are in the exploration of computational techniques for run-time hardware control and optimization of digital and mixed-signal systems over a range of applications. His group’s current research spans clocking, voltage-regulation, power management, baseband processing, ultra-low power electronics, thermal sensing and management, and closed-loop bi-directional neural interfaces.
Visvesh is the recipient of an NSF Career award in 2019 and the Intel outstanding researcher award in 2021. He serves on the technical program committee of the IEEE Custom Integrated Circuits Conference, the Design Automation Conference, the SSCS Webinar committee, and as a distinguished lecturer of the Solid-State Circuits Society.
- Distinguished Lecturer, Solid-State Circuits Society, 2021-2022 (IEEE)
- Outstanding Researcher Award, 2020, Intel
- CAREER Award, 2019, National Science Foundation (NSF)
- Best paper award, “MATIC: Learning around errors for Efficient Neural Network Accelerators”, ACM/IEEE Design Automation and Test in Europe (DATE)
- Vice-President Spotlight Award for the research, development, and translation of resonant-clocking into volume microprocessor production, April 2012, Advanced Micro Devices
C-H. Huang, Y. Chen, X. Sun, A. Mandal, R. Pamula, N. Kurd, V. S. Sathe, “Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control”, Invited paper: the ISSCC special edition of the IEEE J. Solid-State Circuits (JSSC), Jan 2022.
S. Yi; X. Tang, L. Shen, W. Zhao, X. Xin, S. Liu, Z. Zhu, V. S. Sathe, and Sun, Nan “A 10-bit 120-MS/s SAR ADC with Reference Ripple Cancellation Technique”, Invited paper: the CICC special edition of the IEEE J. Solid-State Circuits (JSSC). vol 55, no. 3, pp. 680 – 692. Mar. 2020.
F. Rahman, R. Pamula, A. Boora, X. Sun and V. S. Sathe, “Computationally-Enabled Total Energy Minimization under Performance Requirements for a Voltage Regulated 0.38–0.58V Microprocessor in 65nm CMOS” IEEE J. Solid-State Circuits (JSSC). vol 55, no. 2, pp. 494-504. Feb. 2020.
W. A. Smith, J. P. Uehlin, S. I. Perlmutter, J. C. Rudell, V. S. Sathe, “A 0.0023mm2/ch. Delta-Encoded, Time-Division Multiplexed, Mixed-Signal Recording Architecture with Stimulus Artifact Suppression”, IEEE Transactions on Bio-medical Circuits and Systems (TBioCAS), vol. 14, no. 2, pp. 319-331. Feb. 2020.
J. P. Uehlin, R. Pamula, A. Smith, S. Perlmutter, V. S. Sathe and J. C. Rudell, “A Single-Chip Bidirectional Neural Interface with High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS”, Invited paper: the ESSCIRC special edition of the IEEE J. Solid-State Circuits (JSSC). vol. 55, no. 7, pp. 1749-1761. Jul. 2020.
X. Sun, F. Rahman, R. Pamula, S. Kim, N. John, V. S. Sathe, “An All-digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 11, pp.3215-3225 Sep. 2019
F. Rahman, S. Kim, N. John, R. Kumar, X. Li, R. Pamula, K. Bowman and V. S. Sathe, “A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains,” IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 4, pp. 1173 – 1184, Apr. 2019. Invited paper: the VLSI Symposium special issue of the Journal of Solid-State Circuits.
R. Pamula, X. Sun, S. Kim, F. Rahman, B. Zhang, and V. S. Sathe, “A 65nm CMOS 3.2-to-86 Mbps 2.58 pJ/b Highly Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction,” IEEE Solid-State Circuits Letters (SSCL), vol. 1, no. 12, pp. 237–240, Dec. 2018. Invited paper: the VLSI Symposium special issue of the Solid-State Circuits Letters.
Last revised October 27, 2022