Photo file: 
Full name: 
Tushar Krishna
Job title: 
Assistant Professor
Technical Interest Groups: Computer Systems and Software
Email address: 
Work phone: 
Klaus 2318

Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech, with an Adjunct appointment in the School of Computer Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2014. Prior to that he received a M.S.E in Electrical Engineering from Princeton University in 2009, and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi in 2007.

Before joining Georgia Tech in 2015, Dr. Krishna worked as a researcher in the VSSAD Group at Intel, Massachusetts for 14 months, designing spatial accelerator architectures and HPC networks. During the course of his Ph.D., he spent three summers at AMD in Seattle (WA) and Sunnyvale (CA), and one summer at the Singapore-MIT Alliance for Research and Technology (SMART) Center in Singapore.

Dr. Krishna's research spans the computing stack: from circuits/physical design to microarchitecture to system software. He has over a dozen publications in leading computer architecture conferences and journals and holds one patent.

Dr. Krishna enjoys creative pursuits, and has dabbled in time-lapse photography, glass flameworking, and building a quadcopter.

Research interests: 
  • Computer Architecture
  • Networks-on-Chip (NoC)
  • Interconnection Networks
  • Reconfigurable Computing and FPGAs
  • Heterogeneous Architectures
  • High-Performance Computing
  • Best Paper Award at the 8th International Symposium on Networks-on-Chip, 2014
  • IEEE Micro Top Picks from Computer Architecture Conferences: 2009 and 2014
  • Princeton Graduate Fellowship 2007-08
  • ICIM Stay Ahead Award for the Best Undergraduate Project in Computer Technology, IIT Delhi, 2007

Tushar Krishna and Li-Shiuan Peh, "Single-Cycle Collective Communication Over A Shared Network Fabric", Proc. of 8th International Symposium on Networks-on-Chip (NOCS), Sep 2014. Best Paper Award

Woo-Cheol Kwon, Tushar Krishna, and Li-Shiuan Peh, "Locality-Oblivious Cache Organization leveraging Single-Cycle Multi-Hop NoCs", Proc. of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar 2014

Tushar Krishna, Chia-Hsin Owen Chen, Sunghyun Park, Woo-Cheol Kwon, Suvinay Subramanian, Anantha P. Chandrakasan, and Li-Shiuan Peh, "Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks", IEEE Computer, 46(10): 48-55, Oct 2013

Tushar Krishna, Chia-Hsin Owen Chen, Woo Cheol Kwon and Li-Shiuan Peh, "Breaking the On-Chip Latency Barrier Using SMART", Proc. of the 19th IEEE International Symp. on High-Performance Computer Architecture (HPCA), Feb 2013. Selected for IEEE Micro Top Pics from the Computer Architecture Conferences.

Sunghyun Park, Tushar Krishna, Chia-Hsin Chen, Bhavya K. Daya, Anantha Chandrakasan, and Li-Shiuan Peh, "Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI", Proc. of the 49th Design Automation Conference (DAC), Jun 2012

Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, and Steven K. Reinhardt, "Towards the Ideal On-chip Fabric for 1-to-Many and Many-to-1 Communication", Proc. of the 44th IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec 2011

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill and D. A. Wood, "The gem5 simulator", SIGARCH Computer Architecture News (CAN), 39(2): 1-7, May 2011

Tushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh and Patrick Chiang, "SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90 nm CMOS", Proc. of the 28th IEEE International Conference on Computer Design (ICCD), Oct 2010

Niket Agarwal, Tushar Krishna, Li-Shiuan Peh and Niraj K. Jha, "GARNET: A Detailed On-Chip Network Model inside a Full-System Simulator", Proc. of the International Symp. on Performance Analysis of Systems and Software (ISPASS), April 2009

Last revised May 9, 2016