Sung Kyu Lim was born and grew up in Seoul, Korea, and moved to Los Angeles with his family at the age of 19. He received B.S. (1994), M.S. (1997), and Ph.D. (2000) degrees all from the Computer Science Department of University of California at Los Angeles (UCLA). During 2000-2001, he was a post-doctoral scholar at UCLA, and a senior engineer at Aplus Design Technologies, Inc.
In August 2001, he joined the School of Electrical and Computer Engineering at Georgia Institute of Technology an assistant professor. He is currently the director of the GTCAD (Georgia Tech Computer Aided Design) Laboratory at the School.
He recently released a CD with his rock band in Los Angeles and spends his leisure time writing/recording music.
- Ph.D., Computer Science, University of California, Los Angeles (UCLA), 2000
- M.S., Computer Science, University of California, Los Angeles (UCLA), 1997
- B.S., Computer Science, University of California, Los Angeles (UCLA), 1994
Professor Lim’s research focuses on the design and optimization of VLSI circuits and systems, including low‑power and high‑performance digital circuits. His work addresses semiconductor scaling, circuit reliability, and energy‑efficient computing. His research group emphasizes advanced methodologies for integrated circuit design and actively involves graduate students in theoretical and experimental work.
Professor Lim’s teaching interests include courses on VLSI design, digital integrated circuits, and advanced semiconductor technology. He emphasizes core concepts in circuit design and system integration at both undergraduate and graduate levels. His instruction supports hands‑on learning and prepares students for emerging challenges in electronic system development and semiconductor device applications.
- Advisory Board Member of ACM Special Interest Group on Design Automation (SIGDA) since 2003
- Technical Program Committee Member of ICCD, ISPD, ISCAS, ASPDAC, and GLSVLSI
- NSF CAREER Award, 2006
- D. H. Kim, K. Athikulwongse, M. Healy, M. Hossain, M. Jung, I. Khorosh, et al., “3D-MAPS: 3D massively parallel processor with stacked memory,” ISSCC – Solid-State Circuits Conference Digest of Technical Papers, 2012.
- D. H. Kim, K. Athikulwongse, and S. K. Lim, “A study of through-silicon-via impact on the 3D stacked IC layout,” Proceedings of the International Conference on Computer-Aided Design, 2009.
- M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, “TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC,” Communications of the ACM, vol. 57, no. 1, 2014.
- S. A. Panth, K. Samadi, Y. Du, and S. K. Lim, “Design and CAD methodologies for low power gate-level monolithic 3D ICs,” Proceedings of the International Symposium on Low Power Electronics and Design, 2014.
- J. Kim, G. Murali, H. Park, E. Qin, H. Kwon, V. Chaitanya, K. Chekuri, N. Dasari, et al., “Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse,” Proceedings of the 56th Annual Design Automation Conference, 2019.