Sudhakar Yalamanchili earned his B.E. degree in Electronics from Bangalore University (1978), and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Texas at Austin (1980,1984). After graduation he joined Honeywell’s Systems and Research Center in Minneapolis where he served as the principal investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. While at Honeywell, Dr. Yalamanchili also served as an adjunct faculty and taught in the Department of Electrical Engineering at the University of Minnesota. He joined the ECE faculty at Georgia Tech in 1989 where he is now Regents Professor and Joseph M. Pettit Professor of Computer Engineering. He is the author of VHDL Starters Guide, 2nd edition, Prentice Hall 2004, VHDL: From Simulation to Synthesis, Prentice Hall, 2000, and co-author with J. Duato and L. Ni, of Interconnection Networks: An Engineering Approach, Morgan Kaufman, 2003.
- Novel computer architectures
- Power and thermal management in high performance systems
- Heterogeneous computer architectures: design and optimization
- Associate Editor, IEEE Transactions on Computers 1996 - 2000
- Associate Editor, IEEE Transactions on Parallel and Distributed Systems, 1997 – 2001
- Associate Editor, IEEE Computer Architecture Letters, 2011-2015
- Distinguished Visitor of the IEEE Computer Society, 1993-1996
- IEEE Fellow
- Co-Director, NSF Industry University Cooperative Research Center on Experimental Research in Computer Systems (CERCS), 2003- 2013
- Member, Research Advisory Group, HyperTransport Consortium (www.hypertransport.org), 2007 – 2012.
Steering Committee, IEEE/ACM International Symposium on Networks on Chip (NOCS), 2015 - -present
- Recent Program Committee Activity: ISCA 2014, MICRO2016, NOCS2016, HPCA2014
Organizing Committee, Department of Energy, Office of Science Workshop on Modeling and Simulation of Exascale Systems and Applications (MODSIM), 2013-2016
D. Kim, J. Kung, S. Chai, S. Yalamanchili, and S. Mukhopadhyay, “Neurocube: A Programmable Digital Neuromorphic Architecture with High Density3D Memory,” IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2016.
Y. Wardi, C. Seatzu, X. Chen, and S. Yalamanchili, “Performance Regulation of Event-Driven Dynamical Systems using Infinitesimal Perturbation Analysis, Nonlinear Analysis: Hybrid Systems, to appear 2016.
J. Wang, A. Sidelink, N Rubin, and S. Yalamanchili, “LaPerm: A Locality Aware Scheduler for Dynamic Parallelism on GPUs”, IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2016.
S. Li, V. Sridharan, S. Gurumurthi, and S. Yalamanchili, “Software-based Dynamic Reliability Management for GPU Applications,” IEEE International Reliability Physics Symposium, April 2016
W. J. Song, S. Mukhopadhyay, and S. Yalamanchili, “Amdahl’s Law for Lifetime Reliability Scaling in Heterogeneous Multicore Processors, IEEE Symposium on High Performance Computer Architecture (HPCA), March 2016.
J. Wang, Z. Dong. G. Riley, and S. Yalamanchili, “FNM: An Enhanced Null-Message Algorithm for the Parallel Simulation of Multicore Systems,” ACM Transactions on Modeling and Simulation, vol. 26. No. 2, August 2015.
W. Song, S. Mukhopadhyay, and S. Yalamanchili, “KitFox: Multi-Physics Libraries for Integrated Power, Thermal, and Reliability Simulations of Multicore Architectures,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, no. 11, November 2015.
H. Xiao, W. Yueh, S. Mukhopadhyay and S. Yalamanchili, “Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures,” IEEE Computer Architecture Letters, October 2015.
J. Kung, Wen Yueh, S. Yalamanchili, and S. Mukhopadhyay, “Post-silicon Estimation of Spatiotemporal Temperature Variations Using MIMO Thermal Filters,” IEEE Transactions on Components, Packaging and Manufacturing Technology, May 2015
Last revised May 10, 2016