Dr. Milor received her B.S. degree in Engineering Physics from the University of California at Berkeley. She received her Ph.D. degree in Electrical Engineering in 1992 from the University of California at Berkeley. Her Ph.D. thesis was on testing of analog and mixed signal circuits.
Prior to joining Georgia Tech, Dr. Milor served as Vice President of Process Technology and Product Engineering at eSilicon Corporation, as Product Engineering Manager at Advanced Micro Devices, Sunnyvale, California, and was a faculty member at the University of Maryland in College Park.
Dr. Milor has over 200 publications on yield and test of semiconductor ICs. Nine papers have over 50 citations in google scholar and eight papers have received “best paper” awards. She has graduated 18 Ph.D. students. She has served as a consultant and expert witness in areas of circuit design, test, and semiconductor manufacturing, and has experience in testifying and depositions.
- Ph.D., Electrical Engineering, University of California, Berkeley, 1992
Professor Milor’s research centers on the theory and application of signal processing and information theory. Her work includes statistical estimation, detection theory, and communication systems, emphasizing performance optimization under uncertainty. She investigates methods to improve data interpretation, processing efficiency, and transmission reliability for advanced electrical and computer engineering systems.
Professor Milor’s teaching concentrates on foundational and advanced topics in electrical and computer engineering, including signal processing, systems theory, and information science at both undergraduate and graduate levels. Her instructional approach integrates theory with practical applications, fostering analytical and problem‑solving skills. She is committed to engaging students in research‑driven learning experiences that enhance understanding of modern electrical engineering principles and methodologies.
- IEEE Fellow
- Keynote Addresses at the Design of Circuits and Integrated Systems Conference (2001), TI Yield Conference (2012), CRAW/CDC/NSF Discipline Specific Workshop on Diversity in Design Automation (2014), and IEEE CEDA Spain Chapter/NANOVAR Workshop (2017)
- 8 Best paper awards, including the 2004 Best Paper in the IEEE Transactions on Semiconductor Manufacturing
- Associate Editor for the IEEE Transactions on Computer-Aided Design (2022-present)
- Member of many Technical Program Committees and General Chair for the North Atlantic Test Workshop (2009-2010)
- Best Industrial Mentor Award (1997 from the SRC and 1996 from AMD)
- NSF Career Grant, 1995
- L. Milor, S. Ghosh, “Calibration and efficient evaluation of electromigration lifetime for interconnect wire sizing of multi‑port networks,” Microelectronics Reliability 150, 115163, 2023.
- R. Zhang et al., “A comprehensive framework for analysis of time‑dependent performance‑reliability degradation of SRAM cache memory,” IEEE Transactions on VLSI Systems 29(5), 857–870, 2021.
- R. Zhang et al., “CacheEM: For reliability analysis on cache memory aging due to electromigration,” IEEE TCAD, 2021.
- S.H. Hsu et al., “Optimal sampling for accelerated testing in 14 nm FinFET ring oscillators,” Microelectronics Reliability 114, 113753, 2020.
- S.H. Hsu et al., “Extraction of wearout model parameters using on‑line test of an SRAM,” Microelectronics Reliability 114, 113756, 2020.