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Photo file: 
Full name: 
Linda S Milor
Job title: 
Professor
Technical Interest Groups: Nanotechnology
Email address: 
Work phone: 
404/894-4793
Fax: 
404.894.4641
Office: 
Klaus 1354

Dr. Milor received her B.S. degree in Engineering Physics from the University of California at Berkeley.  She received her Ph.D. degree in Electrical Engineering in 1992 from the University of California at Berkeley.  Her Ph.D. thesis was on testing of analog and mixed signal circuits.

Prior to joining Georgia Tech, Dr. Milor served as Vice President of Process Technology and Product Engineering at eSilicon Corporation, as Product Engineering Manager at Advanced Micro Devices, Sunnyvale, California, and was a faculty member at the University of Maryland in College Park.

Dr. Milor has over 200 publications on yield and test of semiconductor ICs.  Nine papers have over 50 citations in google scholar and eight papers have received “best paper” awards.  She has graduated 18 Ph.D. students.  She has served as a consultant and expert witness in areas of circuit design, test, and semiconductor manufacturing, and has experience in testifying and depositions.

Research interests: 
  • Reliability modeling for semiconductor circuits
  • Circuit performance modeling and prediction as a function of the characteristics of the manufacturing process, including systematic and random variation
  • Analog and mixed-signal testing
  • Yield modeling and prediction as a function of in-line data, test structure data, and design feature geometries
  • Statistical process modeling and characterization
Distinctions: 
  • IEEE Fellow
  • Keynote Addresses at the Design of Circuits and Integrated Systems Conference (2001), TI Yield Conference (2012), CRAW/CDC/NSF Discipline Specific Workshop on Diversity in Design Automation (2014), and IEEE CEDA Spain Chapter/NANOVAR Workshop (2017)
  • 8 Best paper awards, including the 2004 Best Paper in the IEEE Transactions on Semiconductor Manufacturing
  • Associate Editor for the IEEE Transactions on Computer-Aided Design (2022-present)
  • Member of many Technical Program Committees and General Chair for the North Atlantic Test Workshop (2009-2010)
  • Best Industrial Mentor Award (1997 from the SRC and 1996 from AMD)
  • NSF Career Grant, 1995

T. Liu, C.-C. Chen, and L. Milor, “Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors,” IEEE Trans. Emerging Topics in Computing, vol. 6, no. 2, pp. 219-232, June 2018.

.  F. Ahmed and L. Milor, “On-Line Measurement of Degradation Due to Bias Temperature Instability in SRAMs,” IEEE Trans. VLSI, vol. 24, no. 6, pp. 2184-2194, June 2016.

M. Bashir, C.-C. Chen, L. Milor, D.H. Kim, and S.K. Lim, “Backend Dielectric Reliability Full Chip Simulator,” IEEE Trans. VLSI, vol. 22, no. 8, pp. 1750-1762, Aug. 2014.

F. Ahmed and L. Milor, “Analysis of On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells,” IEEE Trans. VLSI, vol. 20, no. 5, pp. 855-864, May 2012.

M. Choi and L. Milor, “The Impact on the Circuit Performance of Deterministic Within-Die Variation in Nanoscale Semiconductor Manufacturing,” IEEE Trans. Computer-Aided Design, vol. 25, pp. 1350-1367, July 2006.

M. Orshansky, L. Milor, and C. Hu, "Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level cirrection," IEEE Trans. Semiconductor Manufacutring, vol. 17, no. 1, pp. 2-11, Feb. 2004.

M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Computer-Aided Design, vol. 21, no. 5, pp. 544-553, May 2002.

L. Milor, "A tutorial introduction to analog and mixed-signal testing," IEEE Trans. Circuits and Systems II, vol. 45, no. 10, pp. 1389-1407, Oct. 1998.

C.Y. Chao, H-J. Lin, and L. Milor, "Optimal testing of VLSI analog circuits," IEEE Trans. Computer-Aided Design, vol 16, no. 1, pp. 58-77, Jan. 1997.

L. Milor and A. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Trans. Computer-Aided Design, vol. 13, no. 6, pp. 796-813, June 1994.

 L. Milor and V. Visvanathan, “Detection of Catastrophic Faults in Analog Circuits,” IEEE Trans. Computer-Aided Design, vol. 8, no. 2, pp. 114-130, Feb. 1989.

Last revised November 22, 2022