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Full name: 
Linda S Milor
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Technical Interest Groups: Nanotechnology
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Work phone: 
Klaus 1354

Dr. Milor received her B.S. degree in Engineering Physics from the University of California at Berkeley. She received her Ph.D. degree in Electrical Engineering in 1992 from the University of California at Berkeley. Her Ph.D. thesis was on testing of analog and mixed-sginal circuits.

Prior to joining Georgia Tech, Dr. Milor served as Vice President of Process Technology and Product Engineering at eSilicon Corporation, as Product Engineering Manager at Advanced Micro Devices, Sunnyvale, California, and was a faculty member at the University of Maryland in College Park.

Dr. Milor has over 80 publications and four patents on yield and test of semiconductor ICs. She serves as a consultant and expert witness in the areas of circuit design, test, and semiconductor manufacturing, and has experience in testifying and depositions.

Research interests: 
  • Reliability modeling for semiconductor processes
  • Circuit performance (speed) modeling and prediction as a function of the characteristics of a process technology
  • Analog and mixed-signal testing
  • Yield modeling and prediction as a function of in-line data, test structure data, and design features
  • Modeling of process modules (i.e. chemical-mechanical polishing, lithography, etc.)
  • Statistical process modeling and characterization
  • Digital testing
  • 2004 Best Paper in the IEEE Transactions on Semiconductor Manufacturing
  • NSF Career Grant, 1995
  • Member of Technical Program Committees for ISSM (International Symposium on Semiconductor Manufacturing), 2002-present, ICCAD (International Conference on Computer-Aided Design), 2006-present, VTS (International Conference on VLSI Test), 2006-present, ICCD (International Conference on Computer Design), 2007-present, DCIS (Design of Circuits and Integrated Systems Conference), 2007-present, NATW (North Atlantic Test Workshop), 2006-present, IMSTW (International Mixed-Signal Test Workshop), 1998-present
  • Guest editor for IEEE Transactions on Semiconductor Manufacturing, Nov. 1999, special issue on IWSM'98.
  • 1997 SRC Outstanding Industrial Mentor Award
  • AMD's Best SRC Mentor Award, 1996
  • 1999 Best Paper Award, AMD Technical Conference
  • 1990 ICCAD Distinguished Paper for "Optimal Test Set Design for Analog Circuits"

M. Orshansky, L. Milor, and C. Hu, "Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level cirrection," IEEE Trans. Semiconductor Manufacutring, vol. 17, no. 1, pp. 2-11, Feb. 2004.

M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Computer-Aided Design, vol. 21, no. 5, pp. 544-553, May 2002.

L. Milor, "A tutorial introduction to analog and mixed-signal testing," IEEE Trans. Circuits and Systems II, vol. 45, no. 10, pp. 1389-1407, Oct. 1998.

C.Y. Chao, H-J. Lin, and L. Milor, "Optimal testing of VLSI analog circuits," IEEE Trans. Computer-Aided Design, vol 16, no. 1, pp. 58-77, Jan. 1997.

L. Milor and A. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Trans. Computer-Aided Design, vol. 13, no. 6, pp. 796-813, June 1994.

L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Computer-Aided Design, vol. 8, no. 2, pp. 114-130, Feb. 1989.

Last revised August 31, 2020