Photo file: 
Full name: 
Joseph L Hughes
Job title: 
Professor
Technical Interest Groups: Computer Systems and Software, VLSI Systems and Digital Design, Microelectronics/Microsystems
Email address: 
Work phone: 
404/894-2975
Fax: 
404.894.3047
Office: 
VL W405

Joseph L.A. Hughes was born in Colorado Springs, Colorado, and grew up in Kansas City, Missouri; Stuttgart, Germany; and Leavenworth, Kansas; before returning to Colorado Springs at the age of nine. He received the B.S.E.E. degree from Illinois Institute of Technology, Chicago, in 1979, and the M.S.E.E. and Ph.D. degrees from Stanford University in Palo Alto, California, in 1980 and 1986, respectively.

Dr. Hughes joined the Georgia Tech faculty in 1986 as an assistant professor, specializing in integrated circuit design and testing. He has participated in several large research programs, including the NSF-funded Packaging Research Center and a DARPA-funded program on optical communication networks. He was named an associate chair in 1997 and then served as senior associate chair from 2006-2013, with responsibility for managing faculty workload, teaching assignments, class scheduling, program accreditation, and other aspects of academic program operation and administration.

Dr. Hughes is a Fellow of IEEE and of the American Society for Engineering Education. He has been a leader in engineering program development, including Georgia Tech’s computer engineering program and the GT-Savannah programs, assessment and accreditation activities, and engineering education initiatives. He currently serves as a member of the Engineering Accreditation Commission of ABET, Inc., and of the IEEE Committee on Engineering Accreditation Activities.

Research interests: 
  • Educational program assessment
  • Engineering education methods
  • Integrated circuit testing
  • VLSI system design
  • Optical communication networks
Distinctions: 
  • Fellow, Institute of Electrical and Electronics Engineers
  • Fellow, American Society for Engineering Education
  • President, IEEE Education Society, 2007, 2008; society officer, 2003-present
  • ECE Distinguished Educator Award, ECE Division of ASEE, 2005
  • Georgia Tech Outstanding Service Award, 1998
  • Member, Engineering Accreditation Commission of ABET, Inc., 2008-present
  • IEEE program evaluator for computer engineering and electrical engineering, 1995-present
  • Member, IEEE Committee on Engineering Accreditation Activities, 2007-present, and IEEE Accreditation Policy Council, 2008, 2009, 2010
  • Electrical and Computer Engineering Division of ASEE, division officer, 1999-2003
  • Member, Association for Computing Machinery
  • Member, Eta Kappa Nu, Tau Beta Pi, Sigma Xi

L. Wills, J. Auerbach, and J.L.A. Hughes, "Partners in Transitioning to Tech: Supporting Students Who Follow Nontraditional Paths to Engineering Degrees," in Proc. 2006 Frontiers in Education Conference, pg. S4G-3 - S4G-8, 2006. (San Diego, California)

D.L. Soldan, V.P. Nelson, A. McGettrick, J. Impagliazzo, P. Srimani, M.D. Theys, and J.L.A. Hughes, "Development of the Model Curriculum for Computer Engineering," in Proc. 2004 Frontiers in Education Conference, pg. F3B-2 - F3B-7, 2004. (Savannah, Georgia)

J.L.A. Hughes, C. Bourgeois, and W.R. Callen, "Using Communications Assignments to Improve Students' Preparation for the Major Design Experience," in Proc. 2002 Frontiers in Education Conference, pg. S3D-13, 2002. (Boston, Massachusetts)

J.L.A. Hughes and P.K. Srimani, "Computing Curricula 2001: Computer Engineering," in 2002 ASEE Annual Conference Proceedings, 2002. (Montreal, Quebec, Canada)

P. Srimani, D. Soldan, M. Theys, E. Roberts, J. Hughes, and V. Nelson. "Computing Curricula 2001: Computer Engineering," in Proc. 2001 Frontiers in Education Conference, pg. S1A-1, 2001. (Reno, Nevada)

J.L.A. Hughes and J.D. Frost, "GTREP: A New Model for Expanding the Availability of Engineering Education, " in Proc. 2001 Frontiers in Education Conference, pp. F4B-1 - F4B-6, 2001. (Reno, Nevada)

J.L.A. Hughes, "Incorporating Project Engineering and Professional Practice into the Major Design Experience," in Proc. 2001 Frontiers in Education Conference, pp. F3G-16 - F3G-21, 2001. (Reno, Nevada)

M. Shell and J.L.A. Hughes, "Performance of All-Optical Shared Memory Architecture Packet Switch Networks Using Channel Grouping Under Bursty Traffic," in Proc. 2001 IEEE Workshop on High Performance Switching and Routing, 2001, pp. 208 - 212. (Dalla, Texas)

Hughes, J.L.A., Enbody, R., and Rover, D., "Towards a More Collegial and Consultative ABET Visit," Proc. 1999 Frontiers in Education Conference, San Juan, Puerto Rico, November 1999.

Bergstrom, P.D., Jr., Ingram, M.A., Vernon, A.J., Hughes, J.L.A., and Tetali, P., "A Markov Chain Model for an Optical, Shared Memory, Packet Switch," IEEE Trans. Communications, October 1999.

Hughes, J.L.A., and Sayle, W.E., "Engineering Criteria 2000 Challenges for Large Programs," 1998 ASEE Annual Conference Proceedings, Seattle, Washington, June 1998.

Yoon, H., Chatterjee, A., Swaminathan, M., and Hughes, J.L.A., "Catastrophic Fault Diagnosis for Embedded MCM RF-Passives Using Single Point Probing," Proc. MCM Test IV Advanced Technology Workshop, Napa, California, September 1997.

Yoon, H., Chatterjee, A., and Hughes, J.L.A., "Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits," Proc. 10th International Conference on VLSI Design, pp. 393-397, Hyderabad, India, January 1997.

Joseph L.A. Hughes, U.R. Khan, H.L. Owen: "Interconnect Networks and Routing Strategies in FPGA-Based Hardware Emulators," Journal of Microelectronic Systems Integration, vol. 3, no. 3, pp. 159-172, 1995.

V.K. Agarwal, A. Chatterjee, Joseph L.A. Hughes, K. Sasidhar: "Distributed Probabilistic Diagnosis of MCMs on Large Area Substrates," Proceedings of the 1995 International Test Conference, pp. 208-216, 1995.

Joseph L.A. Hughes, D.S. Wills: "An Integrated Core Sequence in Digital Computation," Proceedings of the 1995 Frontiers in Education Conference, pp. 2a6.1-2a6.4, 1995.

Hughes, J.L.A., "Multiple Fault Detection Using Single Fault Test Sets," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-7, no. 1, pp. 100-108, January 1988.

Last revised May 9, 2016