Rev. Dr. Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997, and she received her Master of Divinity degree from the Candler School of Theology at Emory University in 2020. Her ordination service was held on December 17, 2021.
Dr. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Dr. Hasler has lived.
Dr. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering.
Dr. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.
- Ph.D., Computation and Neural Systems, California Institute of Technology
- M.Div., Theology, Emory University
- B.S. & M.S.E., Electrical Engineering, Arizona State University
Hasler’s research centers on low power electronics, mixed-signal system ICs, floating-gate MOS transistors, adaptive information processing systems, “smart” interfaces for sensors, cooperative analog-digital signal processing, device physics related to submicron devices or floating-gate devices, and analog VLSI models of on-chip learning and sensory processing in neurobiology.
Hasler’s teaching interests encompass electrical and computer engineering topics and its intersection with neuroscience. She emphasizes student engagement at both undergraduate and graduate levels.
- 2011 Georgia Tech Outstanding Doctoral Thesis Advisor Award 2002 Office of Naval Research Young Investigator. Paul Raphorst best paper award, IEEE Electron Devices Society, 1997 Finalist for the Packard Foundation Young Investigator Fellowships Guest Edit
- First Computational Crossbar / Synaptic Crossbar array (1994)
- Innovation and Naming of Computing in Memory (ARVLSI 2001). (also called In-Memory Computing)
- Experimental Verification (CICC 2004) of Mead’s 1990 Hypothesis that analog computing is thousands more energy efficient than digital computation
- Innovation and development of large-scale Field Programmable Analog Arrays (FPAA) (2002-present), including the first System-on-Chip (SoC) FPAAs and FPAA synthesis tools
- Transistor Channel Model (2002-present) using subthreshold transistors to realiistically model biological channels, neurons, synapses, and dendrites as in computational neuroscience
- Afolabi Ige, Jennifer Hasler, ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs, 2025. DOI: 10.23919/date64628.2025.10993219
- Jennifer Hasler, Praveen Raj Ayyappan, An Analog Architecture and Algorithm for Efficient Convolutional Neural Network Image Computation, Journal of Low Power Electronics and Applications, 2025. DOI: 10.3390/jlpea15030037
- Praveen Raj Ayyappan, Afolabi Ige, Pranav O. Mathews, Linhao Yang, Jennifer Hasler, A 16nm pFET Floating Gate Transistor Enabling Programmable Analog Design in a FinFET Logic CMOS Process, 2025. DOI: 10.1109/esserc66193.2025.11214091
- Jennifer Hasler, Afolabi Ige, Linhao Yang, Pranav O. Mathews, Synthesizing Analog & Mixed-Signal Floating-Gate enabled Reconfigurable Fabrics using Analog Standard Cells, 2025. DOI: 10.1109/iccad66269.2025.11240838