Professor Naeemi received his B.S. degree in electrical engineering from Sharif University, Tehran, Iran in 1994, and his M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, Ga. in 2001 and 2003, respectively.
Prior to his graduate studies (from 1994 to 1999), he was a design engineer with Partban and Afratab Companies, both located in Tehran, Iran. He worked as a research engineer in the Microelectronics Research Center at Georgia Tech from 2004 to 2008 and joined the ECE faculty at Georgia Tech in fall 2008.
His research crosses the boundaries of materials, devices, circuits, and systems investigating integrated circuits based on conventional and emerging nanoelectronic and spintronic devices and interconnects. Dr. Naeemi serves as the leader of the beyond-CMOS benchmarking research at the Semiconductor Research Corporation (SRC) Nanoelectronics Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network (STARnet). He is the recipient of the IEEE Electron Devices Society (EDS) Paul Rappaport Award for the best paper that appeared in IEEE Transactions on Electron Devices during 2007. He has received an NSF CAREER Award, an SRC Inventor Recognition Award, and several best paper awards at international conferences.
- Emerging nanoelectronic devices and circuits
- Spintronic devices and interconnects
- Carbon nanotube and graphene devices and interconnects
- Circuit and system implications of emerging devices
- Design and optimization for nanoscale technologies
- Richard M. Bass/Eta Kappa Nu Outstanding Teacher Award - selected by the vote of the ECE senior class, 2014
- ECE Outstanding Junior Faculty Member Award
- 2014 NSF CAREER Award, 2013
- General Co-Chair, IEEE Int. Interconnect Technology Conf., 2013
- SRC Inventor Recognition Award, 2010
- IEEE EDS Paul Rappaport Award, 2008
- Senior Member, IEEE
- Colonel Oscar P. Cleaver Award, given by the School of ECE at Georgia Tech, 2000
A. Naeemi and J. D. Meindl, "Electron transport modeling for junctions of zigzag and armchair graphene nanoribbons," IEEE Electron Device Letters, vol. 29, pp. 497-499, May 2008.
Book Chapter: A. Naeemi and J. D. Meindl, "Carbon nanotube interconnect modeling,' in Carbon Nanotube Electronics, J. Kong and A. Javey (Eds.), Springer 2008.
A. Naeemi and J. D. Meindl, "Design and performance modeling for single-wall carbon nanotubes as local, semi-global, and global interconnects in gigascale integrated systems," IEEE Trans. Electron Devices, vol. 54, pp. 26-37, January 2007.
R. Sarvari, A. Naeemi, and James. D. Meindl, "Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks," IEEE Intl. Interconnect Technology Conf., June 2005, pp. 197-199.
A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)," IEEE Electron Device Letters, vol. 26, pp. 84-86, Feb. 2005.
A. Naeemi, R. Venkatesan, and J. D. Meindl, "Optimal global interconnects for GSI," IEEE Trans. Electron Devices, vol. 50, pp. 980-987, April 2003.
Last revised August 16, 2017