Arijit Raychowdhury was appointed as the Steve W. Chaddick School Chair in the School of Electrical and Computer Engineering (ECE) at Georgia Tech, effective December 1, 2021. He previously held the Motorola Solutions Foundation Professorship. He joined the ECE faculty as an associate professor in January 2013 and held the ON Semiconductor Junior Professorship from 2015 to 2019.
As the School’s chief academic officer, Raychowdhury oversees a School that is consistently ranked as one of the nation’s most prominent programs of its kind in both graduate and undergraduate education. The School of ECE is one of the largest producers of electrical and computer engineers in the United States, with more than 2,500 undergraduate and graduate students and approximately 100 faculty members.
He is currently the director of the Center for the Co-Design of Cognitive Systems (CoCoSys), a Joint University Microelectronics Program 2.0. Prior to joining Georgia Tech, Raychowdhury held research positions at Intel Corporation for six years and at Texas Instruments for one-and-a-half years. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2007. His research interests include low power digital and mixed-signal circuit design, design of specialized accelerators, power converters, signal-processors, and exploring the interactions of circuits with device technologies. His significant contributions to the semiconductor industry include the design of the world’s first adaptive echo-cancellation network for integrated DSLs at Texas Instruments, and several foundational technologies in memory and logic design at Intel that have been widely used in the industry.
Raychowdhury holds more than 27 U.S. and international patents and has published over 250 articles in journals and refereed conferences. He is currently a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS) and the site director for the DoD-sponsored SCALE Workforce development program in SoC Design. He serves on the Technical Program Committees and Organization Committees of key circuits and design conferences, including ISSCC, VLSI Symposium, DAC, and CICC.
Raychowdhury and his students have won 14 best paper awards over the years. He is the winner of several prestigious awards, including the Semiconductor Research Corporation’s Technical Excellence Award in 2021, Qualcomm Faculty Awards in 2021 and 2020, IEEE/ACM Innovator under 40 Award in 2018, Roger P. Webb Outstanding Junior Faculty Award in 2018, Intel Young Faculty Award in 2015, the NSF CISE Research Initiation Initiative Award (CRII) in 2015, Intel Labs Technical Contribution Award in 2011, Dimitris N. Chorafas Award in 2007, the Best Thesis Award from the College of Engineering at Purdue University in 2007, and several fellowships. Raychowdhury is a Fellow of the IEEE.
- Design of low power digital circuits with emphasis on adaptability and resiliency
- Design of voltage regulators, adaptive clocking, and power management
- Device-circuit interactions for logic and storage
- Alternative compute architectures
- IEEE Fellow, 2022
- SRC Technical Excellence Award, 2021
- Qualcomm Faculty Award, 2021, 2020
- IEEE/ACM Innovator under 40 Award, 2018
- Roger P. Webb Outstanding Junior Faculty Award, 2018
- Intel Young Faculty Award, 2015
- NSF CISE Research Initiation Initiative Award (CRII), 2015
- Intel Labs Technical Contribution Award, 2011
- Dimitris N. Chorafas Award, 2007
- Best Thesis Award from the College of Engineering at Purdue University, 2007
- Gold Medal for the Best Undergraduate of the Year, Jadavpur University, India, 2001
A. Raychowdhury, D. Somasekhar, J. Tschanz, and V. De, "A fully-digital phase-locked low dropout regulator in 32nm CMOS," Proceedings of the VLSI Circuit Symposium, June 2012.
A. Raychowdhury, B. Geuskens, K. Bowman, J. Tschanz, S.-L. Lu, T. Karnik, M. Khellah, V. De, "Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays," Journal of Solid State Circuits (JSSCC), Vol-46, Issue 4, April 2011.
A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S.-L. Lu, V. De, M. Khellah, "PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction," Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.
A. Raychowdhury, D. Somasekhar, T. Karnik, V. De, "Design Space and Scalability Exploration of 1T-1STT MTJ Memory Arrays in the Presence of Variability and Disturbances," Digest of International Electron Device Meeting (IEDM), Dec. 2009.
S. Kumar Gupta, A. Raychowdhury and K. Roy, "Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy," Journal of Applied Physics, Vol. 105, Issue 9, 2009.
Last revised February 3, 2023