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Photo file: 
photograph of Arijit Raychowdhury
Full name: 
Arijit Raychowdhury
Job title: 
Professor
; Motorola Solutions Foundation Professor
Technical Interest Groups: VLSI Systems and Digital Design
Email address: 
Work phone: 
404/894-1789
Office: 
Klaus 2362

Arijit Raychowdhury is currently a Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where he currently holds the Motorola Solutions Foundation Professorship. He joined Georgia Tech in January 2013. From 2013 to July 2019, he was an Associate Professor and held the ON Semiconductor Junior Professorship in the department. Prior to joining Georgia Tech, he held research positions at Intel Corporation for six years and at Texas Instruments for one and a half years. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2007. His research interests include low power digital and mixed-signal circuit design, design of power converters, signal-processors, and exploring interactions of circuits with device technologies. His significant contributions to the semiconductor industry include the design of the world’s first adaptive echo-cancellation network for integrated DSLs at Texas Instruments, and several foundational technologies in memory and logic design at Intel that have been widely used in the industry. Dr. Raychowdhury is currently the director for the IEN Center for Circuits and Systems and the co-director of the Georgia Tech Quantum Alliance.

Dr. Raychowdhury holds more than 27 U.S. and international patents and has published over 250 articles in journals and refereed conferences. He is currently a Distinguished Lecturer of the IEEE Solid State Circuits Society (SSCS) and a mentor for IEEE Young Professionals and IEEE Women in Circuits. He is the site director for the DoD sponsored SCALE Workforce development program. He serves on the Technical Program Committee of key circuits and design conferences including ISSCC, VLSI Symposium, DAC, and CICC, where he is currently serving as the Program Chair. He is the winner of several prestigious awards, including the SRC Technical Excellence Award 2021, Qualcomm Faculty Award 2020, IEEE/ACM Innovator under 40 Award, the NSF CISE Research Initiation Initiative Award (CRII) 2015, Intel Labs Technical Contribution Award 2011, Dimitris N. Chorafas Award for outstanding doctoral research and best thesis 2007, and several fellowships. He and his students have won 13 best paper awards over the years.

 

Research interests: 
  • Design of low power digital circuits with emphasis on adaptability and resiliency
  • Design of voltage regulators, adaptive clocking, and power management
  • Device-circuit interactions for logic and storage
  • Alternative compute architectures
Distinctions: 
  • SRC Technical Excellence Award, 2021
  • Qualcomm Faculty Award, 2020
  • IEEE/ACM Innovator under 40 Award, 2018
  • NSF CISE Research Initiation Initiative Award (CRII), 2015
  • Senior Member, IEEE, 2013
  • Intel Labs Technical Contribution Award, 2011
  • Dimitris N. Chorafas Award for outstanding doctoral research, 2007
  • Best Thesis Award, College of Engineering, Purdue University, USA, 2007
  • Best Paper Awards: International Symposium on Low Power Electronic Design (ISLPED) 2012,2006; IEEE Nanotechnology Conference, 2003
  • SRC Technical Excellence Award, Research Team Member, 2005
  • Intel Foundation Fellowship 2006, NASA INAC Fellowship 2004, Meissner Fellowship 2002

A. Raychowdhury, D. Somasekhar, J. Tschanz, and V. De, "A fully-digital phase-locked low dropout regulator in 32nm CMOS," Proceedings of the VLSI Circuit Symposium, June 2012.

A. Raychowdhury, B. Geuskens, K. Bowman, J. Tschanz, S.-L. Lu, T. Karnik, M. Khellah, V. De, "Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays," Journal of Solid State Circuits (JSSCC), Vol-46, Issue 4, April 2011.

A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S.-L. Lu, V. De, M. Khellah, "PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction," Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.

A. Raychowdhury, D. Somasekhar, T. Karnik, V. De, "Design Space and Scalability Exploration of 1T-1STT MTJ Memory Arrays in the Presence of Variability and Disturbances," Digest of International Electron Device Meeting (IEDM), Dec. 2009.

S. Kumar Gupta, A. Raychowdhury and K. Roy, "Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy," Journal of Applied Physics, Vol. 105, Issue 9, 2009.

Last revised November 5, 2021

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