Photo file: 
Full name: 
Abhijit Chatterjee
Job title: 
Professor
Technical Interest Groups: VLSI Systems and Digital Design, Computer Systems and Software
Email address: 
Work phone: 
404/894-1880
Fax: 
404.894.9846
Office: 
Klaus 1352

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received six Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC).

Dr. Chatterjee has authored over 400 papers in refereed journals and meetings and has 20 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. He is currently directing research in mixed-signal/RF design and test funded by NSF, SRC, MARCO-DARPA, and industry, and he served as chair of the VLSI Technical Interest Group at Georgia Tech from 2010-2012. He co-leads the Samsung Center of Excellence in High-Speed Test established at Georgia Tech in 2011.

Research interests: 
  • VLSI and mixed-signal testing
  • Fault tolerant computing
  • Low power circuit design
  • Computer algorithms
  • Digital automation
Distinctions: 
  • Best Paper Award, Design and Test, ICCD, Boston, MA, November 1992. § NSF Research Initiation Award, 1993.
  • Prof. A. K. Choudhary Best Paper Award, IEEE VLSI Design Symp., Calcutta, India, January 1994.
  • Elected to Senior Member IEEE, February 1994.
  • NSF CAREER Award, 1995.
  • Named Collaborating Partner in NASA's New Millenium Project, 1995.
  • Received Outstanding Faculty for Technology Transfer Award, 1995-1996, Packaging Research Center, Georgia Tech, October 1996.
  • Received the Best Panel Award from the 1996 VLSI Test Symposium, for organizing the most outstanding panel at the conference.
  • Nominated for the Best Paper Award, IEEE VLSI Design Symposium, Bombay, India, and January 1993.

Abhijit Chatterjee, N. Nagi, P. Variyam, H. Yoon: "Hierarchical Statistical Inference Model for Specifcation Based Testing of Analog Circuits," Proceedings, VLSI Test Symposium, pp. 145-150, 1998.

Abhijit Chatterjee, H.T. Nguyen, R.K. Roy: "Activity Measures for Fast Relative Power Estimation Directed Numerical Transformation for Low Power DSP Synthesis," Journal of VLSI Signal Processing Systems, Special Issue on Systematic Trade-off Analysis in Signal Processing Systems Design, vol. 18, no. 1, pp. 25-38, 1998.

Abhijit Chatterjee, P. Variyam: "Enhancing Test Effectiveness for Analog Circuits Using Syntesized Measurements," Proceedings, VLSI Test Symposium, pp. 132-137, 1998.

Abhijit Chatterjee, H.T. Nguyen, R.K. Roy: "Partial Reset Methodologies for Improving Random-pattern Testability and BIST of Sequential Circuits," Proceedings, International Conference on VLSI Design, pp. 199-204, 1998.

J.A. Abraham, Abhijit Chatterjee, N. Nagi: "Signature Analysis for Analog and Mixed-signal Circuit Test Response Compaction," IEEE Transactions of Computer-aided Design, vol. 17, no. 6, pp. 540-545, 1998.

Abhijit Chatterjee, P. Variyam: "Generalized Approach for Test Point Selection in Analog and Mixed-signal Circuits using Measurement Synthesis," International Test Synthesis Workshop, 1998.

Abhijit Chatterjee, J. Hou: "CONCERT: A Concurrent Fault Simulator for Analog Circuits," IEEE International Mixed-signal Testing Workshop, 1998.

Abhijit Chatterjee, R. Pendurkar, Y. Zorian: "A Novel DFT Scheme for Performance Testing of MCMs," International Test Synthesis Workshop, 1998.

Abhijit Chatterjee, P. Variyam: "Test Stimulus Generation for Analog Circuits Using Genetic Optimization," IEEE International Mixed-signal Testing Workshop, 1998.

Abhijit Chatterjee: "Fault Modeling, Fault Simulation, and Test Generation for Mixed-signal Circuits," presented at National Semiconductor Corp., Santa Clara, CA, 1998.

Abhijit Chatterjee, W. Kao, R. Voorakaranam: "AHDL-based Analog Behavioral Fault Modeling and Simulation," Proceedings, Analog and Mixed-signal Applications Conference, pp. 93-96, 1997.

A. Chatterjee, B. Kim, Madhavan Swaminathan: "A Survey of Test Techniques for MCM Substrates," chapter in Multi-chip Module Test Strategies, edited by Y. Zorian, ISBN 0-7923-9920-X, Kluwer Academic Publishers, 1997.

Abhijit Chatterjee, S. Cherubal, V. Gomes, R. Voorakaranam: "Hierarchical Fault Simulation of Feedback Embedded Analog Integrated Circuits with Approximately Linear to Quadratic Speedup," International Mixed-signal Testing Workshop, pp. 48-59, 1997.

A. Chatterjee, J. Hughes, Madhavan Swaminathan, H. Yoon: "Catastrophic Fault Diagnosis for Embedded MCM RF-Passives Using Single Point Probing," IMAPS Advanced Technology Workshop on MCM Test IV, 1997.

Nguyen, H. T., Chatterjee, A., and Roy, R. K., "Activity Measures for Fast Relative Power Estimation Directed Numerical Transformations for Low Power DSP Synthesis," Journal of VLSI Signal Processing Systems, Special Issue on Systematic Trade-off Analysis in Signal Processing Systems Design, 1997.

Abhijit Chatterjee, J.L.A. Hughes, M. Swaminathan, H. Yoon: "Catastrophic Fault Diagnosis for Embedded RF Passives Using Single Point Probing," IMAPS Advanced Technology Workshop on MCM Test IV, 1997.

Abhijit Chatterjee, P. Variyam: "Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient Response Sampling," Proceedings, International Conference on Computer-aided Design, pp. 382-385, 1997.

S. Chakrabarti, Abhijit Chatterjee, S. Cherubal, V. Gomes, J. Hou, W. Kao, R. Voorakaranam: "Hierarchical Specification-driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis," Proceedings, International Test Conference, pp. 903-912, 1997.

Abhijit Chatterjee, R.K. Roy: "Concurrent Error Detection in Non-linear Digital Circuits Using Time-freeze Linearization," IEEE Transactions on Computers, vol. 46, no. 11, pp. 1208-1218, January, 1997.

Kim, B., Swaminathan, M., Chatterjee, A., and Schimmel D., "A Novel Test Technique for MCM Substrates," IEEE Transactions on Components and Packaging Technology, Part B: Advanced Packaging, Vol. 20, No. 1, pp. 2-12, February 1997.

Swaminathan, M., Kim, B., and Chatterjee, A., "A Survey of Test Techniques for MCM Substrates," Journal of Electronic Testing: Theory and Applications, Letter of final acceptance received, November 1996.

Crnic, F., Swaminathan, M., Chatterjee, A., Kim, B., and Koppolu, S., "Electrical Test of MCMs," Chapter in Microsystems Packaging Handbook, Edited by Tummala, R., and Rymaszewski, E., Van Nostrand Reinhold, 1996.

A. Chatterjee, B. Kim, Madhavan Swaminathan: "High Resolution and Low-Cost Test Technique for Unpopulated MCM Substrate," 46th Electronics Technology and Components Conference Proceedings, pp. 225-233, 1996.

Chatterjee, A., Kim, B., and Nagi, N., "Low Cost DC Built-in Self-Test of Linear Analog Circuits," IEEE Design and Test of Computers, summer 1996, pp. 26-33.

A. Chatterjee, B. Kim, Madhavan Swaminathan: "Electrical Interconnect Test Technique for MCM," International Conference on Emerging Microelectronics and Interconnection Technologies Proceedings, Bangalore, India, pp. 285-290, 1996.

A. Chatterjee, B. Kim, D. Schimmel, Madhavan Swaminathan: "A Novel Low-Cost Approach to MCM Interconnect Test," International Test Conference, Washington, DC, 1995.

A. Chatterjee, B. Kim, Madhavan Swaminathan: "A New Technique for Testing MCM Substrates," 2nd Advanced Technology Workshop on MCM Test, 1995.

A. Chatterjee, B. Kim, Madhavan Swaminathan: "A Novel MCM Interconnect Test Technique Based on Resonator Principles and Transmission Line Theory," 4th Topical Meeting on Electrical Performance of Electronic Packaging Proceedings, pp. 117-119, 1995.

V.K. Agarwal, A. Chatterjee, J.L.A. Hughes, K. Sasidhar: "Distributed Probabilistic Diagnosis of MCMs on Large Area Substrates," Proc. International

Chatterjee, A., and Roy, R. K., "Concurrent Error Detection in Non-Linear Digital Circuits Using Time-Freeze Linearization," IEEE Transactions on Computers, 1995.

V.K. Agarwal, A. Chatterjee, Joseph L.A. Hughes, K. Sasidhar: "Distributed Probabilistic Diagnosis of MCMs on Large Area Substrates," Proceedings of the 1995 International Test Conference, pp. 208-216, 1995.

A. Chatterjee, B.C. Kim, David E. Schimmel, M. Swaminathan: "A Novel Low-Cost Approach to MCM Interconnect Test," Proceedings of the International Test Conference, 1995.

Last revised May 16, 2016

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