Updates on the campus response to coronavirus (COVID-19)

ECE Course Syllabus

ECE6140 Course Syllabus


Digital Systems Test (3-0-0-3)

Lab Hours
0 supervised lab hours and 0 unsupervised lab hours

Technical Interest
VLSI Systems and Digital Design

Course Coordinator



Catalog Description
Course covers the science of digital systems testing, fault models, algorithms for fault simulation and test generation, design for testability and built-in self-test.

Abramovici, Breuer & Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1995. ISBN 9780780310629 (required)

Indicators (SPIs)
SPIs are a subset of the abilities a student will be able to demonstrate upon successfully completing the course.

Outcome 1 (Students will demonstrate expertise in a subfield of study chosen from the fields of electrical engineering or computer engineering):
Enter one or two course-specific replacements for Outcome 1: Upon successful completion of the course, the student should be able to: 
1.	Apply a fault simulation algorithm to combinational logic that produces a list of detected stuck-at faults given a set of test vectors for the circuit. Concurrent and deductive fault simulation algorithms are commonly used for such problems.

Outcome 2 (Students will demonstrate the ability to identify and formulate advanced problems and apply knowledge of mathematics and science to solve those problems):
1.	Apply a test stimulus generation algorithm such as D-ALG or PODEM to generate tests for targeted stuck-at faults in combinational circuits.

Outcome 3 (Students will demonstrate the ability to utilize current knowledge, technology, or techniques within their chosen subfield):
1.	Design a Linear Feedback Shift Register (LFSR) to perform Signature Analysis (serve as a single-input signature register).

Topical Outline
 1. Motivation - why test ?
 2. Failure mechanisms and yield models
    a. parametric vs. catastrophic faults
    b. impact of scaled technologies
 3. Theory of digital stuck-at fault testing
    a. basic concepts
    b. fault excitation and sensitization
    c. redundant faults and coverage
    d. multiple faults
 4. Circuit and fault simulation methods
    a. digital circuits, parallel, deductive and concurrent
    b. analog circuits
 5. Test generation algorithms and test methods
    a. digital, stuck-at and delay faults
    b. delay fault testing
    c. analog/RF
 6. Memory Testing
    a. March tests
    b. Testing for pattern sensitive failures
 7. Current based testing methods
 8. Design for testability techniques
    a. scan
    b. JTAG, boundary scan
    c. test response compression
 9. Built-in self-test
    a. LFSR theory 
    b. built-in test architectures
10. Self-calibration techniques
    a. post manufacture circuit tuning for repair/yield-enhancement
11. New topics in test
    a. analog/mixed-signal circuit testing
    b. testing of deeply scaled CMOS devices
12. test methods for neuromorphic networks