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ECE Course Syllabus

ECE6100 Course Syllabus


Advanced Computer Architecture (3-0-0-3)

Lab Hours
0 supervised lab hours and 0 unsupervised lab hours

Technical Interest
Computer Systems and Software

Course Coordinator

ECE 3057/ECE 3058


Catalog Description
Comprehensive coverage of the architecture and system issues that confront the design of a high performance workstation/PC computer architectures with emphasis on quantitaive evaluation. Credit is not allowed for both ECE 6100 and any of the following courses: ECE 4100, CS 4290, CS 6290.

Hennessey & Patterson, Computer Architecture: A Quantitative Approach (6th edition), Morgan Kaufmann, 2017. ISBN 9780128119051 (required)

Indicators (SPIs)
SPIs are a subset of the abilities a student will be able to demonstrate upon successfully completing the course.

Outcome 1 (Students will demonstrate expertise in a subfield of study chosen from the fields of electrical engineering or computer engineering):
1.	Design and analyze pipelined processors with advanced techniques such as out-of-order execution and speculation
2.	Design cache-based memory systems for both uniprocessors and multiprocessors

Outcome 2 (Students will demonstrate the ability to identify and formulate advanced problems and apply knowledge of mathematics and science to solve those problems):
1.	Analytically model latency and throughput for processors and caches

Outcome 3 (Students will demonstrate the ability to utilize current knowledge, technology, or techniques within their chosen subfield):
1.	Understand the implication of Moore's Law / Technology Scaling on performance and power of modern processors

Topical Outline
1. Pipelines    
   a. review basic principles, hazards, dependencies   
   b. Data hazards, scoreboards, Tomasulo algorithm  
   c. control hazards, branch prediction techniques    
   d. multiple instruction issue   
   e. compiler support   
   f. speculative execution         
   g. performance evaluation   
2. Memory systems   
   a. review of caches principles   
   b. techniques to reduce cache misses, multi-level caches    
   c. techniques to reduce hit time 
   d. techniques to improve main memory performance   
   e. virtual memory   
3. Storage Systems (6)  
   a. review of storage technologies, magnetic disk basics    
   b. I/O performance measures, benchmarks   
   c. reliability, availability, RAID  
   d. interaction with caches, OS   
4. Parallel Computers    
   a. taxonomy of parallel architectures, parallel applications                      
   b. synchronization mechanisms    
   c. bus based cache coherence protocols   
   d. directory based cache coherence protocols   
   e. memory consistency models, relaxed consistency models   
   f. interconnection networks, bi-section bandwidth, topologies   
   g. networked workstation cluster computers