ECE Course Outline

ECE4273

Design Synthesis of Application-Specific Signal Processors (2-3-3)

Prerequisites
ECE 4270
Corequisites
None
Catalog Description
Fundamentals of theory and practice of DSP chip design in VHDL. Exposure to tools and environments for chip design, simulation, and verification.
Textbook(s)
Meyer-Baese, Uwe, Digital Signal Processing with Programmable Gate Arrays (3rd edition), Springer, 2008. ISBN 9783540726128 (required)

Topical Outline
[6 hours]   Introduction to DSP processors and ASICs
                Transformational and Reactive Systems
                Charactersitics of DSP applications
                Characteristics of DSP architectures

[9 hours]        DSP Datapath Design
                   Arithmetic Unit Design
                   Pipelining issues and control
                   Flow graph optimizations
                   Examples

[15 hours]         VHDL Language Fundamentals
                    Language fundamentals
                    Simulation-based Design
                    Laboratory issues

[9 hrs]             Register Transfer Level Chip Design
                        FSM models
                        Synthesis issues
                        Verification

[3 hrs]           Filter and FFT chip designs

[3 hrs]                Exams