Note: This assignment has two parts, the first part is simple, you just have to run an existing VHDL simulation using the Altera CAD tools and understand the results. The second part, adding Pipelining to the model will take a significant effort, so be sure to start work early to be able to finish on time. The Altera tools are available in the PC labs, on the web, and a CDROM can be checked out in CoC 360. The MIPS VHDL source files can be downloaded using the link:
1. Use VHDL to synthesize the MIPS single clock cycle design in the file TOP_SPIM.VHD. After synthesis and simulation perform the following steps:
Display and print the timing diagram from the simulation. Verify that the information on the timing diagram shows that the hardware is functioning correctly. Examine the test program in IFETCH.VHD. Look at the program counter, the instruction bus, the register file and ALU outputs, and control signals on the timing diagram and carefully follow the execution of each instruction in the test program. Label the important values for each instruction on the timing diagram and attach a short write-up explaining in detail what the timing diagram shows relative to each instruction's execution and correct operation.
Return to the simulator and run the simulation again. Examine the ALU output in the timing diagram window. Zoom in on the ALU output after execution of the fourth instruction and see what happens when it changes values. Explain exactly what is happening at this point. Hint: Real hardware has timing delays.
2. Pipeline the MIPS VHDL simulation. Test your VHDL model by running a simulation of the example program shown in Figures 6.31-6.35 in Computer Organization and Design The Hardware/Software Interface. To minimize changes, pipeline registers must be placed in the VHDL module that generates the input to the pipeline. As an example, all of the pipeline registers that store control signals must be placed in the control module. Synthesize and check the control module first, since it is simple to see if it works correctly when you add the pipeline flip-flops. Use the following notation to add new latched signals, add a "D_"in front of the signal name to indicate it is the input to a D flip-flop used in a pipeline register. Signals that go through two D flip-flops would be "DD " and three would be "DDD_". As an example, D_instruction would be the registered version of the signal instruction.
Add pipeline registers to the existing modules that generate the inputs to the pipeline registers shown in the text. This will prevent adding more modules and will not require extensive changes to the TOP_SPIM module. Add signal and process statements to model the pipeline modules - see the PC in the ifetch.vhd module for an example of how this can work. A few muxes may have to be moved to different modules.
The control module should contain all of the control pipeline registers - 1, 2, or 3 stages of pipeline registers for control signals. Some control signals must be reset to zero, so use a D flip-flop with a synchronous reset for these pipeline registers. This generates a flipflop with a Clear input that will be tied to Reset. Critical pipeline registers with control signals such as regwrite or memwrite should be cleared at reset so that the pipeline starts up correctly. The MIPS instruction ADD $0, $0, $0 is all zeros and does not modify any values in registers or memory. It is used to initialize the IF/ID pipeline at reset.
Since only eight registers are implemented in the MIPS VHDL model, use the following modified test program:
Lw $1,1($2)
Sub $3,$4,$5
And $2,$7,$6
Or $4,$4,$5
Add $5,$6,$7
Sections 6.2 and 6.3 of Computer Organization and Design, the Hardware/Software Interface contain additional background information on pipelining. Your simulation should show the major busses just as in part one. You can add other signals as needed. Print out the simulation results. Label the simulation output to indicate how the instructions move through the pipeline. This program does not contain data or branch hazards. Hardware for forwarding and branch flushing will be added in later labs.