Ninad Shahane received the Best Interactive Presentation Award at the 2016 IEEE Electronic Components and Technology Conference (ECTC), held May 31-June 3 in Las Vegas, Nevada.
Shahane received the award for his paper entitled “Modeling, Design and Demonstration of Low-temperature, Low-pressure and High-throughput Thermocompression Bonding of Copper Interconnections without Solders.” He is a Ph.D. student at Georgia Tech currently advised by Rao R. Tummala, the Joseph M. Pettit Chair Professor in Electronics in the School of Electrical and Computer Engineering, and mentored by Vanessa Smet, a research scientist with the 3D Systems Packaging Research Center.
The need for higher I/O density, performance, and miniaturization at low cost in emerging high-performance systems, at lower power consumption, is projected to drive off-chip interconnection pitches to 20µm and below in the coming years. This requirement has been reinforced through recent trends towards complex packaging solutions such as 2.5D interposer packages and 3D IC integration in advanced mobile and computing applications. This aggressive pitch scaling has pushed solder-based interconnections, including the current copper (Cu)-pillar technology, to their limits in electrical and thermal performance, as well as processability and reliability with risks of solder bridging and stress management challenges.
As a result, solid-state bonding technologies have gained momentum to address the pitch scaling grand challenge. All-Cu interconnections have been highly sought after by the semiconductor industry as the ultimate interconnection node for their superior electrical and thermal performance, at low cost. Direct Cu-Cu bonding, however, faces three main fundamental challenges: 1) copper oxidation, 2) low-diffusivity of Cu at low assembly temperatures, and 3) high elastic modulus, giving low tolerance to non-coplanarities and warpage. Current approaches consequently rely heavily on sub-micron planarization by chemical-mechanical polishing (CMP), or complex surface activation treatments, escalating costs and limiting their applicability to wafer-level processing only. New solutions are therefore required to address these fundamental and manufacturability challenges.
This paper focuses on mitigating these challenges through a fundamental engineering of the bonding interfaces by applying thin noble surface finish metallurgies on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly at <200oC while retaining the properties of bulk all-Cu interconnections.
School of Electrical and Computer Engineering
Last revised November 13, 2017