Paragkumar Thadesar won first place in the student paper competition at the 2nd Annual IEEE Global Interposer Technology Workshop, held November 14-16 at the Georgia Tech Global Learning Center. A Ph.D. student in the School of Electrical and Computer Engineering (ECE), he is advised by Muhannad Bakir.
The title of Mr. Thadesar's award winning poster was "Silicon Interposer Featuring Novel Low-Loss Through-Silicon Vias Using Polymers." System interconnection has emerged as the key performance limiter in modern computing systems. To obtain high-bandwidth communication between silicon chips, the concept of silicon interposer has been widely explored as it enables multiple silicon chips to be interconnected using dense lateral metallization using BEOL CMOS processing. Silicon interposers consist of vertical interconnects (through-silicon vias (TSVs)) to connect the silicon chips to an organic substrate. Conventional TSVs have large losses and present major challenges. To overcome those issues, Mr. Thadesar and his colleagues fabricated and characterized, for the first time, novel polymer enhanced TSVs that promise more than 10x reduction in TSV insertion losses at 25 GHz.
Last revised August 1, 2017