ECE Graduate Students Win SRC TECHCON Best in Session Awards

Atlanta, GA
Paragkumar Thadesar

Paragkumar Thadesar

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Paragkumar Thadesar and Uppili Raghunathan won Best in Session Awards for their technical areas at the 2013 SRC TECHCON, held September 9-10 in Austin, Texas. Thadesar and Raghunathan are both Ph.D. students in the School of Electrical and Computer Engineering (ECE) at Georgia Tech.

Thadesar won the top award for the 3D-IC Reliability and Optimization session for his paper titled "Fabrication and Wideband Characterization of Novel Photodefined Polymer-Embedded Vias for Silicon Interposers," which he cowrote with his Ph.D. advisor, ECE Associate Professor Muhannad Bakir.

In his paper, Thadesar discusses the transition to multicore microprocessors, which has led to an increasing bandwidth demand between integrated circuits. Using a silicon interposer to interconnect multiple silicon chips and obtain high-bandwidth communication between the chips has been a topic of great interest to both the semiconductor industry and academia. Vertical interconnects, also known as through-silicon vias (TSVs), help connect silicon chips over the silicon interposer to an organic substrate below the interposer, but these state-of-the-art TSVs exhibit a large electrical loss. To address this challenge, Thadesar fabricated and characterized photodefined polymer-embedded vias and proved their scalability for the first time. The polymer-embedded vias promise approximately 80 percent reduction in TSV insertion loss at 50 GHz compared to the state-of-the-art TSVs with similar dimensions.

Raghunathan won the top award for the Analog Devices and Performance session for his paper titled "Identifying SOA Boundaries in SiGe HBTs through Mixed-Mode Device Degradation," which he co-wrote with his fellow ECE graduate students Partha Chakraborty and Brian Wier and his Ph.D. advisor, ECE Professor John Cressler.

Raghunathan and his team study the degradation of SiGe HBTs under mixed-mode electrical stress and identify safe operating areas (SOA) using a physics-based TCAD degradation model that simulates the probabilities of hot energetic carriers acquiring sufficient energies to cause damage at oxide interfaces. They carefully calibrate the avalanche generation model across temperature and calibrate the damage at various points on the I-V output plane to adequately cover it and analyze the SOA boundaries. The team looks at the region of the output plane dominated by high electric field damage and shows boundaries for the SOA at the high-current and low-voltage/low-current limits. They also show the time and temperature dependencies of the two boundaries and the implications this method of determining SOA has for circuit designers.

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Last revised August 1, 2017