Nasir, Raychowdhury Selected for Top Pick Paper in Hardware and Embedded Security

Atlanta, GA
Saad Bin Nasir

Saad Bin Nasir

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A paper coauthored by Saad Bin Nasir and Arijit Raychowdhury has been selected as a “Top Pick Paper in Hardware and Embedded Security.” Both of them are affiliated with the Georgia Tech School of Electrical and Computer Engineering (ECE); Nasir is a recent ECE Ph.D. graduate and Raychowdhury is a professor in the School and served as Nasir’s advisor.  

The “top picks” in hardware security represent the top 10 most impactful papers that have been published in the area in the last six years, from 2013 to 2018. Top pick papers span a gamut of topics in hardware, microarchitecture, and embedded security from leading conferences. They are selected from conference and journal papers that have appeared in leading hardware security conferences, including but not limited to DAC, DATE, ICCAD, HOST, VLSI Design, CHES, ETS, VTS, ITC, IEEE S&P, Euro S&P, Usenix Security, ASIA CCS, NDSS, ISCA, HASP, MICRO, ASPLOS, HPCA, ACSAC, and ACM CCS. 

Nasir’s top-pick paper is titled “High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain” and had previously won the best paper award in the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) in 2017. This paper proposed a novel power management technique that reduces side channel leakage in cryptographic engines. The work was done in collaboration with researchers from Purdue University and continues to have a significant impact in the community. Parts of the design have been adopted by Intel and Qualcomm as a part of their hardware-security roadmap. 

Nasir graduated with his Ph.D. in December 2017 while working in the Integrated Circuits and Systems Research Lab under the advisement of Raychowdhury. Nasir is currently a researcher in Qualcomm’s Corporate Research Division in San Diego, California.

Last revised October 24, 2019