Moinuddin Qureshi will receive the Persistent Impact Prize at the 10thAnnual Non-Volatile Memory Workshop (NVMW). A professor in the Georgia Tech School of Electrical and Computer Engineering, Qureshi will be presented with the award at NVMW on March 12, 2019, in San Diego, California.
The NVMW Persistent Impact Prize is awarded annually to a paper published at least five years prior that has had exceptional impact on the fields of study related to non-volatile memories. Qureshi’s paper, “Scalable High-Performance Main Memory System using Phase Change Technology,” originally appeared at the 36th Annual International Symposium on Computer Architecture (ISCA-36) in June 2009. This paper was co-authored with his IBM colleagues, Viji Srinivasan and Jude Rivers.
This paper was one of the very first architecture proposals to argue for increasing the memory capacity by using Phase Change Memory (PCM). In particular, Qureshi and his co-authors argued that the practical adoption of PCM is viable as main memory only when PCM is combined with DRAM to form a hybrid memory system; DRAM can mitigate the latency and endurance issues of NVM by filtering out majority of the accesses. The hybrid design proposed in this paper almost a decade ago is now the default architecture used while designing NVM-based systems. For systems announced with Optane memory, the NVM does not replace DRAM, but rather resides beside a DRAM cache or DRAM memory. Credited with creating a sub-field in the architecture community on the topic of NVM, this paper has received more than 1,200 citations since publication.
The award selection noted that “the award is given in recognition of the paper's contribution to hybrid memory systems that combine phase change memory and DRAM. It was one of the very first papers to propose such a system and describe how careful design can overcome the limitations of both technologies to build scalable, fast, reliable memory systems. It is especially exciting to see how the paper anticipated and influenced the structure of many subsequent proposals for hybrid memory systems.”
School of Electrical and Computer Engineering
Last revised October 23, 2020