John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.
The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.
Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.
“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”
Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.
After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.
Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."
Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).
“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”
Last revised February 15, 2018