Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies
In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.
With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).
Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.
The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.
Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.
“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.
“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”
This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies. Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.
- Christa M. Ernst
Last revised January 26, 2018