Shreya Dwarakanath won the Best of Track (Advanced Packaging) & Best Student Paper awards at the 49th International Symposium on Microelectronics (IMAPS), held October 10-13, 2016 in Pasadena, California.
Dwarakanath received the award for her paper entitled “Electrodeposited copper-graphite composites for low-CTE integrated thermal structures.” As an award winner, she is invited to attend the IMAPS 2017 Symposium in Raleigh, North Carolina, where she will receive her award. Dwarakanath is a Ph.D. student in the Georgia Tech School of Materials Science and Engineering, and she is advised Professor Rao R. Tummala and mentored by Senior Research Engineer Raj M. Pulugurtha, both of Tech’s School of Electrical and Computer Engineering.
Emerging high-power and high-temperature electronic modules require thick copper (Cu) structures for power-supply, thermal vias, heat-spreaders, and also as carriers or lead-frames for high-power packages. Such structures should coexist with glass and other low-CTE substrates to meet high-temperature performance, dimensional stability, and superior device interconnection reliability with low stresses and warpage. The primary challenge with these packages arises from the coefficient of thermal expansion (CTE) mismatch between the conductors and the substrates.
In order to address this challenge, Cu-graphite composites with glass-matched CTE were explored through analytical modeling of properties such as CTE, Young’s modulus and thermal conductivity, FEM predictions of glass warpage and stresses, process development to deposit copper-graphite composite films with high graphite loading, and warpage measurements using shadow-moiré. Results indicate that Cu-graphite composites can mitigate the warpage and stress issues in high-temperature and high-power packages.
School of Electrical and Computer Engineering
Last revised August 1, 2017