Photo file: 
Full name: 
Joseph A Connelly
Job title: 
Professor Emeritus
Email address: 
Work phone: 
404/894-2911
Fax: 
404.894.4239
Office: 
VL W327

Professor Connelly is no longer supervising new students or projects. Please do not contact him as a potential advisor.

Dr. J. Alvin Connelly received the B.S., M.S., and Ph.D. degrees from the University of Tennessee in 1964, 1965, and 1968 respectively.

At the Georgia Institute of Technology he has developed courses in the areas of analog CMOS and bipolar integrated circuit design, operational amplifiers, low-noise circuit and system design, frequency synthesizers, and advanced electrical measurements.

He is co-author of the books, Macromodeling with SPICE published by Prentice Hall, Low Noise Electronic System Design published by Wiley Interscience, and Analog Integrated Circuits, also published by Wiley Interscience. He has been a consultant to Harris Semiconductor, Signetics Corp., Scientific Atlanta, Honeywell, and GEC Avionics in the general area of analog electronics.

Dr. Connelly serves as an expert witness in these technical areas. He was elected Fellow of IEEE and is a member of many technical and honorary societies and has held various elected offices in the Atlanta Section of IEEE including Section Chair. He is a Registered Professional Engineer in the State of Georgia.

Research interests: 
  • CMOS and bipolar integrated circuit design
  • Macromodeling of analog/digital systems
  • Low noise circuit and system design
  • Phase locked loops
Distinctions: 
  • Fellow of IEEE (1993) "for leadership in integrating industrial analysis and design methodology into engineering education".
  • IEEE Centennial Medalist, 1984 · Greater Atlanta Engineer in Education Award, 1985
  • Eta Kappa Nu Outstanding Teacher Award, 1977
  • Chair of Atlanta Section of IEEE, 1981-1982
  • Toastmasters International, CTM, ATM
  • Registered Professional Engineer, Georgia, #9094
  • ABET Program Evaluator for Electrical Engineering, 1987-92
  • Member of Tau Beta Pi, Sigma Xi, Eta Kappa Nu (Life Member), and ODK Leadership Society

Richard Stair and J. Alvin Connelly, "A Current Mode CMOS Voltage Reference", 2000 Southwest Symposium on Mixed-Signal Design, San Diego, CA, pp. 23-26, Feb. 27-29, 2000.

Craig S. Petrie and J. Alvin Connelly, "The Sampling of Noise for Random Number Generation", ISCAS '99, Orlando, FL, pp. VI-26-29, May 30-June 2, 1999.

J. Alvin Connelly, R.W. Sandage: "A 128 x128 Imaging Array Using Lateral Bipolar Phototransistors in a Standard CMOS Process," ISCAS'98, Monterey, CA, May/June 1998, 1998.

J. Alvin Connelly, C.S. Petrie: "A Noise-based Random Bit Generator IC for Applications in Cryptography," ISCAS'98, Monterey, CA, May/June 1998, 1998.

Robert W. Sandage and J. Alvin Connelly, "A 128 x 128 Imaging Array Using Lateral Bipolar Phototransistors in a Standard CMOS Process", TPA15-9, Monterey, CA, May 31-June 3, 1998.

Craig S. Petrie and J. Alvin Connelly, "A Noise-Based Random Bit Generator IC for Applications in Cryptography," ISCAS'98, TAA14-3, Monterey, CA, May 31-June 3, 1998.

J. Alvin Connelly and Waler E. Thain, "A Charge-pump, PLL Model with Phase Noise and Phase Detector Dead Zone," RF Design, pp. 62-73, 1997.

J. Alvin Connelly, W. Thain: "A Charge-pump, PLL Model with Phase Noise and Phase Detector Dead Zone," RF Design, pp. 62-73, 1997.

J. Alvin Connelly, K. Jennings: "Noise Figure Modeling of Bipolar Transistors Using Spice," RF Design, pp. 33-40, 1996.

J. Alvin Connelly, C.S. Petrie: "Modeling and Simulation of Oscillator-Based Random Number Generators," ISCAS '96, vol. 4, pp. 324-427, 1996.

J. Alvin Connelly, R.W. Sandage: "Producing Phototransistors in a Standard Digital CMOS Technology," ISCAS '96, vol. 1, pp. 369-372, 1996.

J. Alvin Connelly, W.E. Thain: "fa Noise Source Streamlines SPICE Simulations," IEEE Circuits and Devices Magazine, vol. 12, no. 3, pp. 22-27, 1996.

J. Alvin Connelly, R.W. Sandage: "A Fingerprint Opto-Detector Using Lateral Bipolar Phototransistors in a Standard CMOS Process," International Conference on Electronic Devices and Models IEDM, pp. 7.6.1-7.6.4, January, 1995.

"Quarter-Square Analog Four-Quadrant Multiplier Using MOS Integrated Circuit Technology," U.S. Patent No. 4,546,275, issued October 8, 1985.

Last revised November 12, 2015