Photo file: 
Full name: 
David E Schimmel
Job title: 
Associate Professor
Technical Interest Groups: VLSI Systems and Digital Design, Computer Systems and Software
Email address: 
Work phone: 
404/894-4575
Fax: 
404.894.9959
Office: 
Klaus 3306

Professor Schimmel was born in White Plains, New York. He received the B.S.E.E. degree and the Ph.D degree from Cornell University in Ithaca New York in 1984 and 1991 respectively. His studies there focused on VLSI technology and systems, computer science and engineering, and parallel numerical linear algebra.

Professor Schimmel joined the Georgia Tech faculty in 1990 and has contributed to the development of curriculum in computer architecture, VLSI design and digital design. He has chaired the Atlanta Chapter of the IEEE Computer Society and has consulted for industry in the areas of computer architecture and digital system design. He is also a youth soccer coach, a Boy Scout leader, and an avid backpacker.

Research interests: 
  • Parallel computer architecture and reconfigurable computing
  • VLSI system design
  • System area computer network design
  • Asynchronous and self-timed system design
Distinctions: 
  • Member, IEEE
  • Member, Tau Beta Pi
  • Member, Eta Kappa Nu

V. Garg, David E. Schimmel: "Mechanisms for Hiding Communication Latency on Data Parallel Architectures," International Conference on Parallel Processing, Orlando, FL, March/April 1998, 1998.

S.M. Chai, S. Patel, David E. Schimmel, S. Yalamanchili: "Power Constrained Design of Multiprocessor Interconnection Networks," IEEE International Conference on Computer Design, Austin, TX, 1997.

Garg, V., Stogner, D., Ulmer, C., Schimmel, D.E., Dislis, C., Yalamanchili, S., and Wills, D.S., "Early Analysis of Cost/Performance Trade-offs in MCM Systems," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, 20(3), pp 308-319, August 1997.

V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D. Scott Wills, S. Yalamanchili: "Early Analysis of Cost/Performance Trade-offs in MCM Systems," IEEE Transactions on Components, Packaging, and Manufacturing Technology, 20(3), pp. 308-319, 1997.

S. Chai, C. Patel, D. Schimmel, Sudhakar Yalamanchili: "Power/Performance Trade-offs in Direct Interconnection Networks," Proceedings of the Workshop on Parallel Computer Routing and Communication, Lecture Notes in the Computer Science Series, Springer-Verlag (pubs), Fall 1997, 1997.

V. Garg, David E. Schimmel: "Performance Modeling of Dense Cholesky Factorization on the MasPar MP-2," Concurrency: Practice and Experience, 9(7), pp. 697-719, 1997.

S. Chai, C. Patel, D. Schimmel, Sudhakar Yalamanchili: "Performance/Power Trade-offs in Multiprocessor Interconnection Networks," Proceedings of the International Conference on Computer Design, 1997.

C. Dislis, V. Garg, David E. Schimmel, D. Stogner, C. Ulmer, D.S. Wills, S. Yalamanchili: "Early Analysis of Cost/Performance Trade-offs in MCM Systems," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, 20(3), pp. 308-319, 1997.

Garg, V., and Schimmel, D.E., "Performance Modeling of Dense Cholesky Factorization on the MasPar MP-2," Concurrency: Practice and Experience, 9(7), pp. 697-719, July 1997.

V. Garg, S. Lacy, D. Schimmel, D. Stogner, C. Ulmer, D.S. Wills, Sudhakar Yalamanchili: "Incorporating Multi-Chip Module Packaging Constraints into System Design," Proceedings of the European Design and Test Conference, 1996.

V. Garg, S. Lacy, David E. Schimmel, D. Stogner, C. Ulner, D.S. Wills, S. Yalamanchili: "Incorporating Multi-Chip Module Packaging Constraints into System Design," Proceedings of European Design and Test 1996, pp. 508-513, 1996.

V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D.S. Wills, Sudhakar Yalamanchili: "Packaging Trade-Offs in the Design of Embedded High Performance Architectures," First International Workshop on HPC Technology for Embedded Applications, 1996.

J.D. Allen, David E. Schimmel: "Improving Memory Performance for Indirect Accesses on SIMD Computers," Proceedings of the 10th International Parallel Processing Symposium, pp. 759-765, 1996.

Gaughan, P.T., Dao, B.V., Yalamanchili, S., and Schimmel, D.E., "Distributed, Deadlock-free Routing in Faulty, Pipelined k-ary n-cubes," IEEE Transactions on Computers, 45(6), pp. 651-665, June 1996.

B.V. Dao, P.T. Gaughan, D.E. Schimmel, Sudhakar Yalamanchili: "Distributed, Deadlock Free Routing in Faulty, Pipelined Direct Interconnection Networks," IEEE Transactions on Computers, vol. 45, no. 6, pp. 651-665, 1996.

B.V. Dao, P.T. Gaughan, David E. Schimmel, S. Yalamanchili: "Distributed, Dead-Lock-free Routing in Faulty, Pipelined k-ary n-cubes," IEEE Transactions on Computers, vol. 45, no. 6, pp. 651-665, 1996.

Allen, J.D. and Schimmel, D.E., "Issues in the Design of High Performance SIMD Architectures," IEEE Transactions on Parallel and Distributed Systems, 7(8), pp. 818-829, August 1996.

V. Garg, S. Lacy, D. Schimmel, D. Stogner, C. Ulmer, D. Scott Wills, S. Yalamanchili: "Incorporating Multi-Chip Module Packaging Constraints into System Design," Proceedings of the 1996 European Design and Test Conference, six pages, Paris, France, 1996.

J.D. Allen, David E. Schimmel: "PE-Based Caches for Indirect Accesses on SIMD Computers," 1996 International Conference on Parallel Processing (ICPP '96), 1996.

V. Garg, David E. Schimmel: "Architectural Support for Inter-Stream Communication in MSIMD Systems," Future Generation Computer Systems, vol. 11, pp. 617-629, 1995.

David E. Schimmel: "Scalable Embedded Computing for Use in Spaceborne Applications: A Vision for High Performance Computing in Space," panel participant in the ICPP 95 Workshop on Scalable Computing, Oconomowoc, WI, 1995.

A. Chatterjee, B. Kim, D. Schimmel, Madhavan Swaminathan: "A Novel Low-Cost Approach to MCM Interconnect Test," International Test Conference, Washington, DC, 1995.

Garg, V. and Schimmel, D.E., "Architectural Support for Inter-Stream Communication in MSIMD Systems," Future Generation Computer Systems, 11(1995), pp. 617-629, November 1995.

A. Chatterjee, B.C. Kim, David E. Schimmel, M. Swaminathan: "A Novel Low-Cost Approach to MCM Interconnect Test," Proceedings of the International Test Conference, 1995.

Allen, J.D., Gaughan, P.T., Schimmel, D.E., and Yalamanchili, S., "Ariadne - An Adaptive Router for Fault-tolerant Multicomputers," Proceedings of the 21st International Symposium on Computer Architecture '94, Chicago, IL, pp. 278-88, April 18-21, 1994.

Last revised May 10, 2016