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ECE Course Syllabus

ECE7102 Course Syllabus


RISC Architectures (3-0-3)

ECE 6100


Catalog Description
An advanced design oriented class studying the design techniques and operational principles of modern Superscalar RISC datapaths.

John Paul Shen and Mikko Lipasti, Modern Processor Design: Fundamentals of Superscalar Design (Beta edition), McGraw Hill, 2002. ISBN 9780072829686 (required)

Topical Outline
A Brief History of Computer Architecture
     - Technology and Architecture      
     - RISC Design Philosophy      
     - Case Study: IBM 801, RISC 2, and MIPS-X     

Exploiting Instruction-Level Parallelism      
     - Hazards and Instruction Scheduling      
     - Instruction Dispatch, Issue, and Retirement      
     - Reorder & Renaming Buffers      
     - Dynamic Scheduling and Speculative Execution      
     - Superscalar versus Superpipelining      
     - Case Study: Motorola PowerPC 620 and DEC Alpha 21164     

Intel 80x86 Instruction Set: A RISC in CISC Clothing      
     - ISA Limits      
     - Runtime ISA Translation      
     - Case Study: AMD T5 and Intel P6     

Compilation Issues      
     - Instruction Set Architecture      
     - Dependency Graphs and Register Allocation      
     - Static Instruction Reordering      
     - Branch Scheduling     

Very Long Instruction Word Architectures      
     - Trace Scheduling      
     - Case Study: Multiflow Trace 

Tomorrow's Microprocessors      
     - Multithreading      
     - Multiprocessor PCs      
     - Case Study: SUN UltraSPARC, HP VLIW