Introduction to Logic Synthesis
Logic synthesis and two-level logic optimization
- Quine-McClusky method for exact optimization, in psuedo-code.
Data structures for logic optimization, Heuristic two-level logic
Binary Decision Diagrams
- BDD theory. Logic operations on large input/output functions using BDDs.
Symbolic Minimization and Encoding Problems
- State minimization and minimal state encoding using symbolic methods.
Multilevel Logic Synthesis
- Representation and minimization of multiple-level logic networks.
Algebraic and Boolean Methods for multilevel logic network minimization
Timing Issues in Multi-Level Synthesis
- Sensitizable paths, false paths and critical paths in logic networks.
- Automated minimization of Finite State Machines.
- Moving of registers, repartitioning the logic network, to obtain a better
Synchronous Logic Synthesis
- Moving of registers to the periphery for logic minimization of larger
logic block; synchronous don't cares.
- Mapping a logic network to a particular standard cell library for a
Introduction to High-level Synthesis
- Describe enabling and strategic technology, application of VLSI circuit
technology to the design and manufacture of computing, communication, and
- Explain hardware modeling issues: representations, hardware languages,
and abstract hardware models such as dataflow and sequencing graphs.
- Explain data-flow models and derivatives, focusing on computation.
Explain control-flow models, which are based on FSM models.
- Describe the Esterel language with its syntax and semantics.
- Compiling language models into abstract models, from which the
architecture can be synthesized. Explain behavioral-level optimization and
- The scheduling problem, relative timing constraints, resource
constraints, and heuristic methods to satisfy these constraints. PDF. Hu's
algorithm, list scheduling, force-directed scheduling.
- Resource dominated circuits, flat and hierarchical graphs, functional and
memory resources. Extensions to concurrent scheduling and binding.
- Synthesis of pipelined circuits, data-path synthesis, control-unit
Dynamic Power management for circuits
- Idleness and power management; clock gating, circuit partitioning,
pre-computation, and data-path gating.
Dynamic Power management for systems
- Frameworks such as ACPI and OnNow, power management policies.
- Components, technology, and design methodologies. Co-design of computers,
embedded systems, reconfigurable systems. Computer-aided co-design: system
modeling, validation and synthesis.