ECE Course Outline

ECE6132

Computer-Aided VLSI System Design (3-0-3)

Prerequisites
ECE 3060
Corequisites
None
Catalog Description
Theory and practice of computer-aided VLSI digital systems design. Logic synthesis, semi-custom VLSI design, high-level synthesis, low power systems and hardware/software co-design. Individual/group projects.
Textbook(s)
De Micheli, Synthesis and Organization of Digital Circuits, McGraw Hill, 1994. ISBN 9780070163331 (required)

Topical Outline
Introduction to Logic Synthesis
Logic synthesis and two-level logic optimization
- Quine-McClusky method for exact optimization, in psuedo-code.
Data structures for logic optimization, Heuristic two-level logic 
optimization
Binary Decision Diagrams
- BDD theory. Logic operations on large input/output functions using BDDs.
Symbolic Minimization and Encoding Problems
- State minimization and minimal state encoding using symbolic methods.
Multilevel Logic Synthesis
- Representation and minimization of multiple-level logic networks.
Algebraic and Boolean Methods for multilevel logic network minimization
Timing Issues in Multi-Level Synthesis
- Sensitizable paths, false paths and critical paths in logic networks.
FSM Optimization
- Automated minimization of Finite State Machines.
Retiming
- Moving of registers, repartitioning the logic network, to obtain a better 
solution.
Synchronous Logic Synthesis
- Moving of registers to the periphery for logic minimization of larger 
logic block; synchronous don't cares. 
Library Binding
- Mapping a logic network to a particular standard cell library for a 
particular process
Introduction to High-level Synthesis
- Describe enabling and strategic technology, application of VLSI circuit 
technology to the design and manufacture of computing, communication, and 
consumer products.
Modeling
- Explain hardware modeling issues: representations, hardware languages, 
and abstract hardware models such as dataflow and sequencing graphs.
Verilog
FSM-based formalisms
- Explain data-flow models and derivatives, focusing on computation. 
Explain control-flow models, which are based on FSM models.
Esterel
- Describe the Esterel language with its syntax and semantics.
Architectural synthesis
- Compiling language models into abstract models, from which the 
architecture can be synthesized. Explain behavioral-level optimization and 
program-level transformations.
Scheduling
- The scheduling problem, relative timing constraints, resource 
constraints, and heuristic methods to satisfy these constraints. PDF.  Hu's 
algorithm, list scheduling, force-directed scheduling.
Resource sharing
- Resource dominated circuits, flat and hierarchical graphs, functional and 
memory resources.  Extensions to concurrent scheduling and binding.
Control synthesis
- Synthesis of pipelined circuits, data-path synthesis, control-unit 
synthesis.
Dynamic Power management for circuits
- Idleness and power management; clock gating, circuit partitioning, 
pre-computation, and data-path gating.
Dynamic Power management for systems
- Frameworks such as ACPI and OnNow, power management policies.
Hardware/Software Co-Design
- Components, technology, and design methodologies. Co-design of computers, 
embedded systems, reconfigurable systems. Computer-aided co-design: system 
modeling, validation and synthesis.