ECE Course Outline


VLSI and Advanced Digital Design (3-3-4)

ECE 2031 [min C] and ECE 2040 [min C]
Catalog Description
Advanced digital design issues in the context of VLSI systems. Introduction to a design methodology that encompasses the range from architectural models to circuit simulation.
Wolf, Modern VLSI Design: IP-Based Design (4th edition), Prentice Hall, 2008. ISBN 0137145004, ISBN 978-0137145003 (required)

Sutherland, Sproull & Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. ISBN 1558605576, ISBN 978-1558605572 (required)

Course Objectives - As part of this course, students:

  1. master the core concepts of digital design in the context of VLSI technology. [a]
  2. master the core concepts in the design of testable and low power digital VLSI systems. [a]
  3. are provided a laboratory-based experience in designing and implementing custom VLSI systems. [a, d]
  4. gain experience with modern VLSI design and layout tools using state-of-the-art facilities. [a, d, e]
Course Outcomes - Upon successful completion of this course, students should be able to:

  1. demonstrate a clear understanding of important concepts in CMOS technology and fabrication that affect design.
  2. design a gate of any given arbitrary logic function at the transistor-level.
  3. layout a gate in CMOS VLSI technology.
  4. size the gates of the given VLSI layout to minimize the delay.
  5. design a network of complex gates with the ideal number of stages that computes the function with ????????????minimum delay.
  6. simulate a VLSI design in SPICE to obtain delay and power performance measures.
  7. find a test vector to test given faults in a logic network.
  8. design and characterize synchronized circuits for asynchronous external inputs.
  9. design and layout a variety of adders and multipliers.
  10. analyze and simulate interconnect delay.
  11. design and layout a datapath that consists of various functional, memory, communication, and interface units.
  12. understand system issues such as floorplanning and power/ground distribution
Topical Outline
1.	Design Methodology (1 week)

2.	Switches and Layout (3 weeks)
   a.	Switch based design
   b.	Complex gates
   c.	Layout and technology
   d.	Registers
   e.	Adders

3.	Ciruit design issues (4 weeks)
   a.	MOSFET models
   b.	Delay models
   c.	Hazards, metastability, synchronization
   d.	Alternate logic structures
   e.	Timing and clocking
   f.	Power models
   g.	Sleep transistors

4.	Advanced digital issues (3 weeks)
   a.	Logical effort
   b.	Ideal number of stages
   c.	Asymmetric gates
   d.	Calibrating the model
   e.	Branches and Interconnect

5.	Test Logic (1 week)
   a.	Combinational test
   b.	Sequential test
   c.	Scan design

6.	Advanced Modules (2 weeks)
   a.	ROM, PLA
   b.	Advanced adders
   c.	Multipliers
   d.	Barrel shifter
   e.	Decoders