Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. He joined the faculty of the Georgia Institute of Technology in September 2007.
Dr. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. Dr. Mukhopadhyay has (co)-authored over 60 papers in reputed conferences and journals and filed four United States patents.
- Low-power, variation tolerant, and reliable VLSI systems
- Device/circuit level modeling/estimation of power, yield, and reliability
- Technology-circuit co-design methodologies
- Self-adaptive systems with on-chip sensing and repair technique
- Memory design for VLSI applications
- Ultra-low power and fault-tolerant nanoelectronics: technology, circuit, and computing platforms
- Office of Naval Research (ONR) Young Investigator Award, 2012
- ECE Outstanding Junior Faculty Member Award, 2012
- Class of 1934 Course Survey Teaching Effectiveness Award, 2012
- National Science Foundation (NSF) CAREER Award, 2011
- IBM Faculty Award, 2009 and 2010
- SRC Inventor Recognition Award, 2008
- IBM Ph.D. Fellowship award in 2004-2005
- 2005 SRC Technical Excellence award as a member of the Purdue University research group
- Best paper awards at IEEE-Nano 2003 and ICCD 2004, Best paper in session award at TECHCON-2005
S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," IEEE Journal Solid-State Circuits (JSSC), vol 42, no. 6, June 2007, pp. 1370 - 1382.
S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy, "Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2007, pp. 400-401.
S. Mukhopadhyay, K. Kim; X. Wang; D. J. Frank, P. Oldiges, C.T. Chuang, and K. Roy, "Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design," IEEE Electron Device Letters (EDL), vol. 27, no. 4, April 2006, pp. 284 - 287.
S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 14, no. 2, Feb. 2006, pp. 183- 192.
S. Mukhopadahyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 12, Dec. 2005, pp. 1859-1880.
S. Mukhopadhyay, A. Raychowdhury, K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," IEEE Transaction on Computer-Aided Design of Integrated Circuits and System (TCAD), vol. 24, no. 3, March 2005 pp. 363 - 381.
Last revised May 9, 2018