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IEEE Circuits and Systems Society Industrial Distinguished Lecture

Event Details

Tuesday, October 26, 2021

2:00pm - 3:30pm

Pettit Microelectronics Building, Rooms 102 A&B

For More Information


Shaolan Li

School of Electrical and Computer Engineering


Event Details

Date: October 26, 2021

Time: 2:00-3:30 pm

Location: Pettit Microelectronics Building, Rooms 102 A&B

Speaker: Debendra Das Sharma

Affiliation: Intel

Title: PCI Express® 6.0: a low latency, high bandwidth, high reliability and cost-effective interconnect with 64.0 GT/s PAM-4 s

Bio: Debendra Das Sharma is an Intel Fellow in the Data Platforms Group and director of the I/O Technology and Standards Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. Das Sharma’s team delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Intel’s Coherency interconnect, and multichip package interconnect. He is a key driver of external standards for PCIe and CXL, and internal proprietary interfaces, as well as implementation. 

Das Sharma joined Intel in 2001 as a technical lead in the Advanced Components Division, designing server chipsets. He previously worked with Hewlett-Packard, where he led development of their server chipsets. He holds 144 US patents. He is a frequent keynote speaker, distinguished lecturer, invited speaker, and panelist at the Hot Interconnects, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Intel Developer Forum.

Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force.

Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur.

Abstract: PCI Express® (PCIe®) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. We propose a new flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism to meet the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels will be deployed to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Registration/More Information: https://events.vtools.ieee.org/m/286511

Last revised October 21, 2021