Ph.D. Proposal Oral Exam - Arvind Singh

Event Details

Wednesday, October 24, 2018

10:00am - 12:00pm

Room 3100, Klaus

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Event Details

Title:  Exploiting On-chip Power Management for Side Channel Security


Dr. Mukhopadhyay, Advisor   

Dr. Krishna, Chair

Dr. Beyah


The objective of the proposed research is to develop side channel analysis attack resistant architectures for lightweight ciphers and design of generic low-overhead countermeasures for Advanced Encryption Standard (AES) hardware engines.  The architectures for a lightweight block cipher SIMON are explored for improved energy efficiency, performance and for increased robustness against side channel attacks. Lightweight countermeasures are further explored and a prototype test-chip with an on-chip integrated inductive voltage regulator (IVR) and all-digital clock modulation scheme to enhance side channel resistance of AES engines is developed. A random fast voltage dithering (RFVD) scheme is proposed to randomize voltage and frequency of operation for the encryption engine at fast and regular steps to scramble power and electromagnetic signatures, therefore, improving the side channel analysis (SCA) attack immunity. An improved random fast voltage dithering (I-RFVD) scheme utilizing enhanced frequency randomization and loop randomizer of the IVR is presented to further increase SCA resistance. Advanced filtering to identify and isolate leakage bands and frequency domain analysis techniques are explored to extract secret encryption key with correlation power analysis (CPA) and correlation electromagnetic analysis (CEMA). The research progress to date demonstrates increased resistance against SCA with IVRs and ADCM, the remaining work will focus on acquiring and analyzing side channel measurements from a prototype test-chip consisting of low dropout regulators.

Last revised October 17, 2018