Ph.D. Dissertation Defense - Juan Pablo Caram Wigdorsky

Event Details

Thursday, October 11, 2018

10:00am - 12:00pm

Room W225, Van Leer

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Event Details

TitlePhase Noise Improvement Techniques for Mixed-mode Phase-locked Loops in Nanometer CMOS


Dr. Stevenson Kenney, ECE, Chair , Advisor

Dr. Stephen Ralph, ECE

Dr. Gregory Durgin, ECE

Dr. Richard Causey, ECE

Dr. Paul Kohl, ChBE


This research presents circuit-level solutions for frequency synthesis and other time-domain signal processing problems. Specifically, three circuit architectures are proposed: a hybrid digital and analog phase-locked loop architecture that is capable of suppressing reference and VCO phase noise simultaneously, a VCO architecture that eases tradeoffs between ring VCOs and LC VCOs, and a time-to-digital converter with a sample-and-hold mechanism, dynamic element matching and quantization noise scrambling.

Last revised September 27, 2018