Professor Hsien-Hsin S. Lee
Spring 2008
Time: TTh @ 3:05 - 4:25pm
Classroom: Van Leer W200
Office hours: TTh 4:45-6pm @Klaus 2318
Course Syllabus
Textbook:
  • Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson. The 4th edition, Morgan Kaufmann. 2006. ISBN 0-12-370490-1.
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    [ Class Announcement | Schedule & Slides | Papers | Assignments | TA Schedule | Discussion Boards | Exams | Honor Code]

    Class Announcement
    01/07: First class meeting.
    01/16: TA Abilash Sekar's hours are post. Start from 01/21. Check Here for the entire schedule.
    01/22: Programming Assignment #1 is out. Due on 02/11.
    02/12: Programming Assignment #2 is out. Due on 03/05.
    02/26: Exam #1 solution is post.
    03/11: Programming Assignment #3 is out. Due on 04/07.
    04/10: Programming Assignment #4 is out. (Not a Simplescalar assignment.) Due on 04/28.
    04/15: Exam #2 solution is post.

    Class Schedule and Slides (Subject to Change)
    Week Topic Slide Lecture Reading Assignment Other Announcement
    1 (01/07-01/11) Performance, Pipelining Lec0-intro.ppt
    Lec1-perf.ppt
    Lec2-pipeline.ppt    		 01/08
    01/10     		Chapter 1, Appendix A, B
    2 (01/14-01/18) ISA Taxonomy Lec3-isa.ppt
    		 01/15
    01/17     		Chapter 2.1-2.2, Chapter 3
    Interesting Paper Readings
    Suggested Paper Readings
    3 (01/21-01/25) ILP Lec4-ilp.ppt 01/22
    01/24     		Chap 2.3
    Mandatory Paper Readings    		 ¥ 01/21: Official Holiday
    ¥ 01/22: PR#1 out
    4 (01/28-02/01) Branch Prediction Lec5-bpred.ppt 01/29
    01/31     		Class note
    Mandatory Paper Readings
    5 (02/04-02/08) High Bandwidth Instruction Fetching Lec6-ifetch.ppt 02/05
    02/07     		Appendix A.7, Sec 2.4 - 2.5
    Suggested Paper Readings
    6 (02/11-02/15) Dynamic Scheduling Lec7-dyn_schedule1.ppt 02/14 Sec 2.6, pp.127-128, A-54-56
    Suggested Paper Readings    		 ¥ 02/11: PR#1 due
    ¥ 02/12: PR#2 out
    7 (02/18-02/22) Tomasulo Algorithm, Register Renaming 02/21 Mandatory Paper Readings ¥ Exam 1 (02/19)
    8 (02/25-02/29) Precise Interrupts, ROB Lec8-dyn_schedule2.ppt 02/26
    02/28    		 Appendix C, Chapter 5
    9 (03/03-03/07) Caches Lec9-mem1.ppt 03/04
    03/06    		 Mandatory Paper Readings ¥ 03/05: PR#2 due
    10 (03/10-03/14) Virtual Memory, TLB Lec10-mem2.ppt 03/11
    03/13    		 Chapter 6
    Suggested Paper Readings    		 ¥ 03/11: PR#3 out
    11 (03/17-03/21) No Class       ¥ Spring Break
    12 (03/24-03/28) DRAM, Storage Systems, P6 Lec11-mem3.ppt 03/25
    03/27    		 Handout of P6
    Mandatory Paper Readings    		  
    13 (03/31-04/04) Netburst, Multithreading, SMT, Multicore, Core Lec12-p6_P4.ppt
    Lec13-multicore.ppt    		 04/01 Chapter 4.1-4.2
    Suggested Paper Readings    		 ¥ Exam 2 (04/03)
    14 (04/07-04/11)  Coherency and Consistency Lec14-coherence.ppt 04/08
    04/10    		 Chapter 4.3-3.8
    Suggested Paper Readings    		 ¥ 04/07: PR#3 due
    ¥ 04/10: PR#4 out
    15 (04/14-04/18) EPIC, Itanium Lec15-EPIC.ppt 04/15
    04/17    		 Mandatory Paper Readings
    16 (04/21-04/25) Modulo Scheduling, Rotating Registers   04/22
    04/24    		 Suggested Paper Reading
    17 (04/28-05/02) Final Exam
    April 30 (Wed)
    11:30 to 2:20pm    		 ¥ 04/28: PR#4 due

    Required Readings
    [RISC versus CISC, Interesting Bedtime Architecture Readings]
  • Instruction Sets and Beyond: Computers, Complexity, and Controversy by Bob Colwell et al., 1985.
  • Response to Colwell's article by David Patterson and John Hennessy, 1985.
  • More controversy: response to the response of Patterson and Hennessy by Colwell et al., 1985.
  • Note that, Bob Colwell later became the chief architect of Intel's Pentium Pro and Pentium 4.
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    [ILP, Suggested]
  • ILP limit paper by David Wall, DEC Tech Report, 1993.
  • ILP limit paper by Matthew Postiff et al. in INTERACT-3, 1999.
  • ILP limit for VLIW / EPIC by Hsien-Hsin Lee et al. in ISPASS, 2000.
    		•
    [Branch Predictors, Mandatory]
  • Branch Correlation paper by S.-T. Pan, K. So and J. Rahmeh in ASPLOS, 1992.
  • Two Level Branch Predictor paper by Tse-Yu Yeh and Yale Patt in ISCA-19, 1992.
  • Combining Branch Predictor by Scott McFarling, 1993.
    		•
    [High Bandwidth Instruction Fetching, Mandatory]
  • Collapsing Buffer paper by Tom Conte et al. in ISCA-22, 1995.
  • Trace Cache paper by Eric Rotenberg, Steve Bennett and Jim Smith in MICRO-29, 1996.
    		•
    [Dynamic Scheduling, Suggested]
  • Tomasulo Algorithm original paper by Robert Tomasulo, IBM Journal, 1967.
    		•
    [Register Renaming, Suggested]
  • Register Update Unit paper by Guri Sohi and Sriram Vijapeyam, ISCA 1987.
  • Register Renaming Design paper by Dezso Sima, IEEE MICRO, 2000.
    		•
    [Dynamic Scheduling, Precise Interrupts, ReOrder Buffer, Mandatory]
  • Precise Interrupts paper by Moudgill and Vassiliadis, IEEE MICRO 1996.
  • ReOrder Buffer for Precise Interrupt paper by Jim Smith and Andy Pleszkun, IEEE Transactions on Computers, 1988.
  • ReOrder Buffer (Retrospective) article by Jim Smith, Selected paper of 25 years of ISCA, 1998.
    		•
    [Cache Memory, Mandatory]
  • Victim cache paper by Norm Jouppi, ISCA-17, 1990.
  • Non-blocking cache paper by David Kroft, ISCA-08, 1981.
  • Assist cache paper by Kenneth Chan et al., Hewlett-Packard Journal, 1996.
  • Cache memory paper by Alan J. Smith, (read Section 2.1.2 Prefetching), Computing Survey, 1982.
    		•
    [DRAM, Suggested]
  • Introduction to DRAM. Source: Book Excerpt from Wiley Publishers
  • Memory Technology Overview by Hewlett-Packard.
  • High Perforamnce DRAMs by Vinodh Cuppu, Bruce Jacob, Brain Davis and Trevor Mudge, IEEE Trans on Computers, 2001.
    		•
    [P4, Mandatory]
  • P4 Microarchitecture paper by Intel Technology Journal, 2001.
    		•
    [SMT, Suggested]
  • Exploiting Choice: SMT instruction fetching paper by Tullsen et al., ISCA 1996.
    		•
    [MP, Suggested]
  • Stanford DASH paper by Dan Lenoski, IEEE Computer, 1992
  • Memory Consistency Model Tutorial by Sarita Adve and Kourosh Gharachorloo, DEC WRL-TR 95/07, 1995
    		•
    [Itanium, Mandatory]
  • IA64 architecture paper by Jerry Huck et al., IEEE MICRO, 2000
    		•
    [Itanium, Suggested]
  • Itanium microarchitecture paper by Sharangpani and Arora, IEEE MICRO, 2000
    		•

    Programming Assignments
    PR#1 (1) Problem Download
    (2) Simplescalar Toolkit
    (3) SPEC2000.make Makefile
    (4) CPU2000int.tgz: includes 6 SPEC2000 integer benchmark applcaitions.
    (5) CPU2000fp.tgz: includes 5 SPEC2000 floating-point benchmark applcaitions.
    (6) redir.sh (CSH) for standard output/err files reduction used by SPEC2000.make.
    (7) redir.sh (SH) use this one if you are running on Cygwin sh shell.
    (8) www.simplescalar.com: Simplescalar website, you can find many instructional documents here.
    PR#2 (1) Problem Download
    (2) Dynamic Branch Prediction with Preceptrons paper
    (3) SPEC2000.make.br : Makefile
    (4) default.cfg : An 8-wide OOO processor configuration.
    (5) test-printf.s and test-fmath.s: disassembled Alpha binaries for debugging purpose (the binaries are in tests-alpha/bin directory)
    (6) alpha-linuxobjdump : objdump utility for Alpha binary (only run on an x86 Linux).
    (7) Use the same Simplescalar framework and benchmark suite of Programming Assignment #1.
    PR#3 (1) Problem Download
    (2) SPEC2000.make.cache
    (3) default.vc.cfg
    (4) Use the same Simplescalar framework, benchmark suites and tools of Programming Assignment #1 and #2.
    PR#4 (1) Problem Download
    (2) Memory Traces: moesi.sp08.tgz

    Discussion Boards
    We use Google Group for posting questions or exchanging thoughts with the group and me. Due to multiple sections, it is more convenient to discuss questions for all in one central place. However, we will use T-square to post grades.

    TA Schedule
    Abilash Sekar abilash.sekar _@_ gatech _._ edu
    Location: Klaus 1440 (look for 6100 TA sign)
    Lab Hours: Check if you have a Google account or Click HERE if you don't.

    Exams
    Exam #1 Solution
    Exam #2 Solution

    Honor Code
  • Students are expected to abide by the Georgia Tech Honor Code and to avoid any instances of academic misconduct in homework assignments and exams. Any violation will be directly reported to the Dean of Students' Affairs for further action. We take this matter seriously!
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  • Please read the Student Code of Conduct. In particular, Section B regarding Prohibited Academic Conduct
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