(in reverse chronological order of graduation)

 
Dr. Peter G. Sassone is a member of Intel's Microprocessor Research Lab (MRL) in Austin, TX.  He received all of his degrees from Georgia Tech -- a Bachelors of Computer Engineering in 2000, a Masters of Electrical and Computer Engineering in 2002, and a PhD in Electrical and Computer Engineering in 2005.  His graduate work focused on characterizing and avoiding micro-architectural bottlenecks in aggressive superscalar procesors such as the issue and bypass loops. He currently continues this work on the micro-architecture of future Intel designs.
Dr. Jongmyon Kim is currently an engineer at the Samsung Advanced Institute of Technology in South Korea. He received his Bachelor of Science in Electrical Engineering from MyongJi University in South Korea in 1995, his Master of Science in Electrical and Computer Engineering from the University of Florida in 2000, and his PhD in Electrical and Computer Engineering in 2005.
Dr. Soo J. Ryu is currently a member of research staff in the i-Networking Lab of Samsung Advanced Institute of Technology in South Korea. She received her B.S. (summa-cum-laude) degree in Computer Science from Dong-Duk Women's University, Korea in 1994. She earned her M.S. in Information and Communication Engineering from Korea Advanced Institute of Science and Technology (KAIST), Korea in 1996 and was employed by KAIST as a research engineer (August 1996 - July 1997) to develop a query optimizer for Spatial DBMS. In 2003, she earned her Ph.D. degree from Georgia Institute of Technology. Her research addressed storage management techniques in embedded SIMD architectures. Her current research interests include embedded processors, memory optimization techniques, reconfigurable compilers, and platform based SoC designs.
 

Dr. William H. Robinson is an Assistant Professor in Electrical Engineering at Vanderbilt University in Nashville, Tennessee. He received his B.S. in electrical engineering from Florida Agricultural and Mechanical University in 1996 and his M.S. in electrical engineering from Georgia Institute of Technology (Georgia Tech) in 1998. He received his Ph.D. in Electrical and Computer Engineering at Georgia Tech in 2003. His research explores the system-level integration of computer architecture to understand the impact of technology on architecture design. Topics of interest include VLSI design, parallel computer architectures, and image processing. He is a 1996 National Science Foundation Graduate Fellow and a 2002 Ford Foundation Dissertation Fellow. His IEEE membership includes both the Computer Society and the Lasers and Electro-Optics Society. Other professional memberships include the American Society of Engineering Educators (ASEE), National Society of Black Engineers (NSBE), and SPIE – The International Society for Optical Engineering.
Dr. Tarek M. Taha is an Assistant Professor in Electrical and
Computer Engineering at Clemson University in Clemson, South
Carolina. He received his Bachelor of Electrical Engineering at
Georgia Tech and Bachelor of Arts at DePauw University, both in
1996. He received his Masters of Electrical Engineering at
Georgia Tech in 1998 and his Ph.D. in Electrical & Computer
Enginering at Georgia Tech in 2002. His research interests
include analytical models of computer architectures, short wire
architectures, GSI semiconductor technology, and portable
multimedia supercomputers. He is a member of the IEEE and the
IEEE Computer Society.
Dr. Mondira Pant (Deb) is currently a hardware engineer in the Alpha Development Group of Compaq Computer Corporation in Shrewsbury, MA. She received her B.Tech degree in Computer Science and Engineering from IIT Kharagpur, India, in 1995. She earned her MSEE and PhD degrees in 1997 and 2000 respectively from Georgia Institute of Technology. Her research addressed the growing problem of on-chip inductive noise in GSI circuits from an architect's standpoint. Her research interests include VLSI design, high-performance architectures and apporaches to solving inductive noise in these systems. She is an currently an IEEE and IEEE Computer Society member.
Dr. Antonio Gentile is currently Assistant Professor at the Department of Automatics and Computer Science of the University of Palermo, Italy. Dr. Gentile received his Dr. Ing. degree (M.S.E.E.) in Electrical Engineering and his doctoral degree in Computer Science from the University of Palermo in 1992 and 1996, respectively. He also received his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta (USA), in 2000, directed by Prof. D. Scott Wills. His research interests include high performance computer architectures, parallel computing, image processing, and VLSI design. Dr. Gentile is member of the Portable Image Computation Architecture (PICA) Group, of the IEEE Society, of the IEEE Computer Society, and of the ACM Society. Dr. Gentile can be contacted at antonio.gentile@unipa.it.
Dr. Lucian Codrescu is a Computer Architect at the Motorola Design Center in Austin, TX. He received his B.S. Computer Engineering from Virginia Tech in 1993. From 1993-1995 he worked as a software engineer with General Electric in the area of embedded Operating Systems. He received his Ph.D. in Electrical and Computer Engineering (2000) from Georgia Tech. His doctoral thesis addresses techniques for parallel execution of sequential programs on a multithreaded architecture including mem-slicing partitioning and data partitioning. His research interests include high performance architectures, architectures for gigascale technologies, and VLSI. He is a member of the IEEE and the Computer Society.
Dr. Kee Shik Chung is a member of the technical staff at Intel Corporation in Chandler, AZ. He received his Ingeniero Electronico diploma from Universidad de Buenos Aires (Argentina) in 1991, and his Master of Science in Electrical Engineering in 1993 from University of Southern California. He received his Ph.D. in Electrical and Computer Engineering (2000) from Georgia Tech. His doctoral research addresses instruction level SIMD Architectures and short wire instruction broadcast for SIMD architectures. Dr. Chung's research interests include Image Processing Architectures, Parallel Computing, Interconnection Networks, and Low Power VLSI Design.
Dr. Phil May is a Senior Staff Engineer at the Digital DNA System Architecture Lab at Motorola in Schaumburg, Illinois. He received his BSE EE from the University of Michigan in 1987. From 1987 until 1994 he was employed by Motorola's Government and Space Technology Group. At Motorola he designed circuits and systems for communications applications. Dr. May completed his Ph.D. in Electrical and Computer Engineering at Georgia Tech in 1999. His research interests include parallel architecture, interconnection networks, and system and circuit design for VLSI.
Dr. Sek Meng Chai Sek Meng Chai (M'99) received the B.S, M.S., and Ph.D. degrees in electrical engineering from Georgia Institute of Technology, Atlanta, in 1994, 1996, 1999, respectively. Currently, he is a Research Engineer at the Multimedia Architecture Laboratory, Motorola Labs, Schaumburg, IL. His research interests include image processing architectures, parallel processors, VLSI, billion transistor SoC, and high-performance interconnection networks. His doctoral research addresses high throughput, efficient architectures such as systolic arrays. He is a member of the IEEE, IEEE Computer Society, and ACM.
Dr. John C. Eble is currently a member of the technical staff at Velio Communications in Chapel Hill, NC. He formally was employed as a staff engineer at Compaq in Shrewsbury, MA. He received his BCmpE in Computer Engineering and MSEE and Ph.D. in Electrical and Computer Engineering from Georgia Tech in 1993, 1994, and 1998 respectively. His doctoral research addressed the development of a generic system simulator, GENESYS, and architectural models for performance and efficiency of microprocessors. His research interests include low-power, high-throughput programmable image processing architectures and generic system and architecture performance modeling. He is a member of the IEEE and ACM.
Dr. James M. Baker Jr. is an Assistant Professor of Electrical and Computer at Virginia Tech. He received his BS and MS degrees in Electrical Engineering from Virginia Tech in 1988 and 1990, respectively. He received his Ph.D. in Electrical and Computer Engineering at Georgia Tech in 1998. His doctoral thesis addressed run-time operating systems for fine-grain parallel architectures. His research interests include computer architecture, parallel processing, and system software. He is a member of the IEEE, the IEEE Computer Society, and the ACM.
Dr. Abelardo López-Lagunas is an assistant professor in the Instituto Tecnologico y de Estudios Superiores de Monterrey Campus Toluca. He received his B.S. in Electrical Engineering from that institution in 1988, his M.S. degree (1991) and Ph.D. (1997) in Electrical and Computer Engineering from the Georgia Institute of Technology. As a graduate student he formed part of the Portable Image Computation Architecture (PICA) group directed by Dr. D. Scott Wills. His doctoral research focused on hardware support for fine-grain architectures. In 1998, he joined the Concurrent VLSI Architecture Group, led by Dr. William J. Dally in the design of the Imagine processor at Stanford. His research interests include Parallel Architectures, VLSI design, and parallel compilers. He is a member of the IEEE and the IEEE Computer Society.
Dr. Michael Hopper is Senior Software Engineer at Fundtech Corporation in Atlanta, Georgia, a provider of OLTP banking applications. He is involved with transaction processing applications on heterogeneous platforms in CORBA, Java, C++, XML, and Oracle. He received his BSEE and MSEE degrees from the University of Alabama in 1989 and 1991. He received his Ph.D. from Georgia Tech in 1997. He is a member of IEEE as well as the Eta Kappa Nu and Tau Beta Pi honor societies.
Dr. W. Stephen Lacy received the B.S. degree in electrical engineering from Christian Brothers University (Memphis, TN) in 1991, and the M.S.E.E. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology in 1993 and 1996, respectively. At Georgia Tech, Dr. Lacy was a founding student member of the Portable Image Computation Architecture (PICA) group where he performed research in fine-grained parallel computing and multicomputer interconnection networks. Dr. Lacy is currently a member of the technical staff at Synopsis in Santa Clara, CA. Dr. Lacy's research interests include VLSI systems design, interconnection networks, and architectures for parallel and distributed computation. Dr. Lacy is a member of the IEEE Computer Society, and of the Tau Beta Pi and Phi Beta Kappa academic honor societies.
Dr. José L. Cruz-Rivera received the B.S.E.E. degree from the University of Puerto Rico-Mayagüez in 1991 (Magna Cum Laude) and the M.S. and Ph.D. degrees in Electrical Engineering from the Georgia Institute of Technology in 1992 and 1996, respectively. Dr. Cruz-Rivera has six years of experience in higher education as a professor of Electrical and Computer Engineering (ECE) at the University of Puerto Rico-Mayagüez (UPRM), where he has served as Associate Director for Research and Academic Affairs of the Electrical and Computer Engineering Department, Director of the Center for Computing Research and Development, and Dean of Academic Affairs. His research interests include high-performance computer architectures, high-performance microprocessor-based systems, optoelectronic technologies, parallel algorithm characterization, and image processing applications.

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