ECVASS: Portable Video Supercomputing

Embedded Parallel Architectures for Multimedia: Portable Video Supercomputing

As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing array of portable products, the need for high efficiency, high throughput embedded processing is becoming an important challenge in computer architecture. Video-centric embedded applications, such wireless videoconferencing, real-time video enhancement and analysis, and new, immersive modes of distance education, demand real-time processing of high bandwidth I/O streams while imposing more restrictive size, weight, and power requirements than desktop computing.

Portable video supercomputing (PVS) systems are low-cost embedded computers that combine supercomputer performance with the high I/O bandwidth needed for video-centric applications and the energy efficiency required for deployment in portable systems.

SIMPil: A low memory, monolithically integrated SIMD architecture which exploits
the substantial data parallelism that exists in video processing applications.

Methodology for exploring processing element design space

This research focuses on the design and evaluation of PVS systems. It uses a novel design methodology that combines application simulation with analytical technology modeling to provide a desired combination of performance, area, and energy consumption. This is critical in designing low-cost, high-performance computer vision systems that are designed to optimally exploit the latest advances in semiconductor technology and the availability of low-cost, high-resolution imaging arrays.

Publications:

W. H. Robinson and D. S. Wills, Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture, Journal of VLSI Signal Processing, Special Issue on System-on-a-Chip for Multimedia Systems, Vol. 41, No. 1, pp. 65-80, August 2005.
A. Gentile, S. Sander, L. M. Wills and D. S. Wills, Impact of Pixel to Processor Ratio in Embedded SIMD Image Processing Architectures, Journal of Parallel and Distributed Computing, Vol. 64, No. 11, pp. 1318-1327, November 2004.
A. Gentile and D. S. Wills, Portable Video Supercomputing, IEEE Transactions on Computers, Vol. 53, No. 8, pp. 960-973, August 2004.
W. H. Robinson and D. S. Wills, Analysis of Area-time Efficiency for an Integrated Focal Plane Architecture, Proceedings for the 15^th Annual Symposium on Electronic Imaging: Science and Technology, Image and Video Communications and Processing 2003, Vol. 5022, SPIE and IS&T, pp. 272-283, Santa Clara, California, January 2003.
W. H. Robinson, G. E. Triplett and D. S. Wills, Component Modeling for an Integrated Digital Pixel, Proceedings for the 15^th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Display and Imaging Systems, pp. 37-38, Glasgow, Scotland, November 2002.
W. H. Robinson and D. S. Wills, Design of an Integrated Focal Plane Architecture for Efficient Image Processing, Proceedings of the 15^th International Conference on Parallel and Distributed Computing Systems (PDCS2002), pp. 128-135, Louisville, Kentucky, September 2002.
A. Gentile, D. S. Wills, J. L. Cruz-Rivera and F. Sorbello, Real-Time, Low Level Image Processing on SIMPil - an Embedded SIMD Architecture, AIIA Notizie, Proceedings of the Italian Association for Artificial Intelligence (AI*IA), Vol. 15, No. 4, pp. 40-43, Bari, Italy, also appeared in Proceedings of the Seventh Conference of the Italian Association for Artificial Intelligence (AI*IA 2001), February 2002.
A. Gentile and D. S. Wills, Impact of Pixel per Processor Ratio on Embedded SIMD Architectures, Proceedings of the 11^th IEEE International Conference on Image Analysis and Processing (ICIAP2001), pp. 204-208, Palermo, Italy, September 2001.
A. Gentile, D. S. Wills and F. Sorbello, A Novel Methodology for the Design of Processing Elements in Embedded SIMD Architectures for Multimedia, Proceedings of the 2001 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA2001), pp. 437-443, Las Vegas, Nevada, June 2001.
W. H. Robinson and D. S. Wills, Cost Modeling for Early Image Processing Applications, Proceedings of the 2^nd Annual International Workshop for Digital and Computational Video, DTV, and HDTV Technology, pp. 29-34, Tampa, Florida, February 2001.
Y. Joo, J. Park, M. Thomas, K. Chung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Smart CMOS Focal Plane Arrays: A Si CMOS Detector Array and Sigma-Delta Analog-to-Digital Converter Imaging System, IEEE Journal of Special Topics in Quantum Electronics, Special Issue on Smart Photonic Components, Interconnect, Processing, Vol. 5, No. 2, pp. 296-305, March 1999.
S. M. Chai, A. Gentile and D. S. Wills, Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor, Proceedings of the 20^th Anniversary Conference on Advanced Research in VLSI, pp. 57-71, Atlanta, Georgia, March 1999.
W. H. Robinson, D. S. Wills, M. A. Brooke and N. M. Jokerst, IRIS: An Integrated, Scalable Focal Plane Architecture, Proceedings of LEOS'98 11^th Annual Meeting, Optical Image Processing, Memory, 3D Interconnects, pp. 184-185, Orlando, Florida, December 1998.
S. Bond, S. Jung, O. Vendier, M. Brooke, N. M. Jokerst, S. Chai, A. Lopez-Lagunas and D. S. Wills, 3D Stacked Si CMOS VLSI Smart Pixels Using Through-Si Optoelectronic Interconnections, Proceedings of the IEEE Lasers and Electro-Optics Society Summer Topical Meeting on Smart Pixels, pp. 27-28, Monterey, California, July 1998.
H. H. Cat, A. Gentile, J. C. Eble, M. Lee, O. Vendier, Y. J. Joo, D. S. Wills, M. Brooke, N. M. Jokerst, A. S. Brown and R. Leavitt, SIMPil: An OE Integrated SIMD Architecture for Focal Plane Processing Applications, Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 44-52, Maui, Hawaii, October 1996.
D. S. Wills, Smart Pixel Architectures for Image Processing, Digest of the IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels, pp. 93-94, August 1996.
D. S. Wills, J. M. Baker, H. H. Cat, S. M. Chai, L. Codrescu, J. Cruz-Rivera, J. Eble, A. Gentile, M. Hopper, W. S. Lacy, A. Lopez-Lagunas, P. May, S. Smith and T. Taha, Processing Architectures for Smart Pixel Systems, IEEE Journal of Selected Topics in Quantum Electronics, Vol. 2, No. 1, pp. 24-34, April 1996.
S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan H. H. Cat, S. Wilkinson, M. Lee, N. M. Jokerst and M. A. Brooke, A Three Dimensional High-Throughput Architecture Using Through-Wafer Optical Interconnect, IEEE/OSA Journal of Lightwave Technology Special Issue on Optical Interconnections for Information Processing, Vol. 13, No. 6, pp. 1085-1092, June 1995.