Testing and Reliability Engineering Lab

"Mixed Signal/Analog/RF Test, Reliability, Yield and Low Power for Next Generation Systems"

School of Electrical and Computer Engineering
Georgia Institute of Technology

  |           Home           |           Faculty           |           Students           |           Projects           |           Publications           |  

Publications List and PDF files for Workshop Papers

(Last Updated: Summer 2004) Following is a list of publications from the lab. Some of these articles are still in process, hence not yet published. You can also click on the links available to get a PDF copy of selected workshop papers. Electronic copies of other articles are available through common sources such as IEEE Explore.

 

Published Journal Articles

  • S. Akbay, A. Halder, A. Chatterjee, and D. Keezer, ``Low cost test of embedded RF/Analog/Mixed-Signal Circuits in SOPs,'' IEEE Trans. on Advanced Packaging, vol. 27, pp. 352-363, May 2004.
    •

 

Journal Articles in Progress

  • A. Halder and A. Chatterjee, ``Test generation for specification test of analog circuits using efficient test response observation methods,'' Micro-electronics Journal. (submitted).
  • G. Srinivasan, S. Bhattacharya, S. Cherubal, and A. Chatterjee, ``Fast specification test of tdma power amplifiers using transient current measurements,'' IEE Proc. Computers and Digital Techniques, special issue on best technical contributions to the proceedings of Design Automation and Test in Europe (DATE) 2004. (to be published).
  • G. Srinivasan, S. Bhattacharya, S. Cherubal, and A. Chatterjee, ``Efficient test strategy for tdma power amplifiers using transient current measurements: Uses and benefits,'' IEE Electronic Letters. (to be published).
  • R. Voorakaranam, S. Cherubal, S. Akbay, and A. Chatterjee, ``Signature testing of analog and RF circuits: Algorithms and methodology,'' IEEE Transactions on Circuits and Systems. (submitted).
  • S. Bhattacharya, A. Halder, G. Grinivasan, and A. Chatterjee, ``Alternate testing of RF transceivers using optimized test stimulus for accurate prediction of system specifications,'' Journal of Electronic Testing: Theory and Applications. (to be published).
  • S. Bhattacharya and A. Chatterjee, ``Wafer-probe and assembled-package test co-optimization to minimize overall test cost,'' ACM Transactions on Design Automation of Electronic Systems. (to be published).

 

Published Conference Articles

  • A. Halder and A. Chatterjee, ``Specification based digital compatible built-in test of embedded analog circuits,'' in Proc. IEEE 10th Asian Test Symposium, Kyoto, Japan, pp. 344-349, November 2001.
  • A. Halder and A. Chatterjee, ``Automated test generation and test point selection for specification test of analog circuits,'' in Proc. IEEE International Symposium of Quality Electronic Design (ISQED), San Jose, CA, USA, pp. 401-406, March 2004.
  • A. Halder, S. Bhattacharya, and A. Chatterjee, ``Automatic multitone alternate test generaton for RF circuits using behavioral models,'' in Proc. IEEE International Test Conference, Charlotte, NC, USA, pp. 665-673, September 2003.
  • A. Halder, S. Bhattacharya, G. Srinivasan, and A. Chatterjee, ``A system-level alternate test approach for specification test of rf transceivers in loopback mode,'' in Proc. 18th International Conference on VLSI Design, Kolkata, India, January 2005. (page numbers not known yet).
  • A. Halder, P. Variyam, A. Chatterjee, and J. Ridley, ``Measuring stray capacitance on tester hardware,'' in Proc. IEEE 20th VLSI Test Symposium, Monterey, CA, USA, pp. 351-356, April 2002.
  • A. Halder and A. Chatterjee, ``Low-cost alternate evm test for wireless receiver systems,'' in Proc. 23rd IEEE VLSI Test Symposium, Palm Springs, CA, USA, May 2005. (to be presented).
  • D. Han and A. Chatterjee, ``Device resizing based optimization of analog circuits for reduced test cost: cost metric and case study,'' in Proc. IEEE Asian Test Symposium, Kenting, Taiwan, pp. 420-425, November 2004.
  • D. Han and A. Chatterjee, ``Adaptive response surface modeling-based method for analog circuit sizing,'' in Proc. IEEE International System-on-Chip Conference, Santa Clara, CA, USA, pp. 109-112, September 2004.
  • G. Srinivasan, S. Goyal, and A. Chatterjee, ``Reconfiguration for enhanced alternate test (realtest) of analog circuits,'' in Proc. 13th Asian Test Symposium, Kenting, Taiwan, pp. 302-307, November 2004.
  • G. Srinivasan, S. Bhattacharya, S. Cherubal, and A. Chatterjee, ``Efficient test strategy for tmda power amplifiers using transient current measurements: Uses and benefits,'' in Proc. Design and Test in Europe, CNIT La Defese, Paris, France, pp. 280-285, February 2004.
  • S. Akbay and A. Chatterjee, ``Feature extraction based built-in alternate test of rf components using a noise reference,'' in Proc. 22rd IEEE VLSI Test Symposium, Napa Valley, CA, USA, pp. 273-278, April 2004.

  • S. Akbay and A. Chatterjee, ``Built-in test of rf components using feature extraction sensors,'' in Proc. 23rd IEEE VLSI Test Symposium, Palm Springs, CA, USA, May 2005. (to be presented).
  • S. Bhattacharya and A. Chatterjee, ``A built-in loopback test methodology for rf transceiver circuits using embedded sensor circuits,'' in Proc. 13th Asian Test Symposium, Kenting, Taiwan, pp. 68-73, Nov 2004.

  • S. Bhattacharya, R. Senguttuvan, and A. Chatterjee, ``Production test method for evaluating the effect of narrow-band interference on data errors in ultra-wide band (uwb) receivers,'' in Proc. IEEE MTT-S International Microwave Symposium, Long Beach, CA, June 2005. (to be presented).
  • S. Bhattacharya and A. Chatterjee, ``Use of embedded sensors for built-in-test of rf circuits,'' in Proc. 35th International Test Conference, Charlotte, NC, pp. 801-809, October 2004.

  • S. Bhattacharya, A. Halder, and A. Chatterjee, ``Automatic alternate test generation for rf circuits using behavioral models,'' in TECHCON Conference, Dallas, TX, USA, August 2003.
  • S. Bhattacharya and A. Chatterjee, ``High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost,'' in Proc. 21st VLSI Test Symposium, Napa Valley, CA, USA, pp. 89-95, April 2003.
  • S. Bhattacharya, G. Srinivasan, S. Cherubal, A. Halder, and A. Chatterjee, ``System-level testing of rf transmitter specifications using optimized periodic bitstreams,'' in Proc. 22nd VLSI Test Symposium, Napa valley, CA, USA, pp. 229-234, April 2004.
  • S. Bhattacharya and A. Chatterjee, ``Production test methods for measuring 'out-of-band' interference of ultra wide band (uwb) devices,'' in Proc. 23rd VLSI Test Symposium, Napa Valley, CA, USA, May 2005. (to be presented).
  • Y. Dhillon, A. Diril, and A. Chatterjee, ``Soft-error tolerance analysis and optimization of nanometer circuits,'' in Proc. Design, Automation and Test in Europe Conference, Munich, Germany, p. (to be presented), March 2005.
  • Y. Dhillon, A. Diril, and A. Chatterjee, ``Algorithm for achieving minimum energy consumption in cmos circuits using multiple supply and threshold voltages at the module level,'' in Proc. International Conference on Computer-Aided Design, San Jose, CA, USA, pp. 693-700, November 2003.
  • Y. Dhillon, A. Diril, A.Chatterjee, and A. Singh, ``Sizing cmos circuits for increased transient error tolerance,'' in Proc. 10th IEEE International On-Line Testing Symposium, Funchal, Madeira Island, Portugal, pp. 11-16, July 2004.
  • Y. Dhillon, A. Diril, A. Chatterjee, and A. Singh, ``Low-power dual vth pseudo dual vdd domino circuits,'' in Proc. 17th Symposium on Integrated Circuits and Systems Design, Porto de Galinhas, Pernambuco, Brazil, pp. 273-277, September 2004.
    •

 

Conference Articles in Progress

  • D. Han and A. Chatterjee, ``Circuit sizing based synthesis of analog circuits for enhanced testability,'' in Proc. 42nd Design Automation Conference, Anaheim, CA, USA, June 2005. (submitted).
  • G. Srinivasan, S. Cherubal, P. Variyam, M. Teklu, C. Wang, D. Guidry, and A. Chatterjee, ``Accurate measurement of multi-tone power ratio (mtpr) of adsl devices using low cost testers,'' in Proc. 10th European Test Symposium, Tallinn, Estonia, May. (submitted).

 

Published Workshop Articles

  • A. Halder, S. Bhattacharya, and A. Chatterjee, ``Alternate test generation for specification test of rf circuits,'' in Proc. IEEE International Mixed-Signal Testing Workshop, Seville, Spain, June 2003.

  • A. Halder and A. Chatterjee, ``Automated test generation and concurrent test point selection for specification based test of analog circuits,'' in Proc. Latin American Test Workshop, Natal, Brazil, February 2003.

  • D. Han, A. Halder, and A. Chatterjee, ``Test elimination using redundancy analysis for specification test of analog circuits,'' in Proc. 10th International Mixed-Signal Test Workshop, Portland, Oregon, USA, pp. 69-75, June 2004.

  • D. Han and A. Chatterjee, ``Simulation-in-the-loop analog circuit sizing method using adaptive model-based simulated annealing,'' in Proc. 4th IEEE International Workshop on System-on-Chip, Banff, Alberta, CANADA, pp. 127-130, July 2004.

  • G. Srinivasan, A. Halder, S. Bhattacharya, S. Goyal, and A. Chatterjee, ``Loopback test of RF transceivers using periodic bit sequences: An alternate test approach,'' in Proc. IEEE International Mixed-Signal Testing Workshop, Portland, OR, USA, June 2004.

  • G. Srinivasan, S. Goyal, and A. Chatterjee, ``Enhancing alternate test performance for analog circuits using reconfiguration for testability,'' in Proc. 5th IEEE Latin-American Test Workshop, Cartagena, Columbia, pp. 134-139, March 2004.

  • M. Ashouei, A. Chatterjee, and A. Singh, ``A test data compression technique and its application to scan,'' in Defect-Based Testing Workshop, April 2004.

  • S. Akbay and A. Chatterjee, ``Temperature compensated built-in alternate test of RF modules,'' in Digest of 1st IEEE International GHz/Gbps Test Workshop, Charlotte, NC, USA, October 2004.

  • S. Akbay and A. Chatterjee, ``Optimal multisine tests for RF amplifiers,'' in Digest of 2nd IEEE Workshop on Test of Wireless Circuits and Systems, International Test Conference, Baltimore, MD, USA, October 2002.

  • S. Akbay and A. Chatterjee, ``Alternate test of RF mixers by current signatures,'' in Digest of 3rd Workshop on Test of Wireless Circuits and Systems, International Microwave Symposium, Fort Worth, TX, USA, June 2004.

  • S. Bhattacharya and A. Chatterjee, ``Constrained specification based test stimulus generation for analog circuits using nonlinear performance prediction models,'' in Proc. 1st International Workshop on Electronic Design, Test Applications (DELTA), Christchurch, New Zealand, pp. 25-29, January 2002.

  • S. Bhattacharya, G. Srinivasan, S. Cherubal, and A. Chatterjee, ``Test time reduction for acpr measurement of wireless transceivers using periodic bit-stream sequences,'' in Proc. 2nd International Workshop on Electronic Design, Test Applications (DELTA), Perth, Australia, January 2004.

  • S. Bhattacharya and A. Chatterjee, ``Wafer probe and assembled package test co-optimization for minimal test cost,'' in Proc. 8th International Mixed-Signal Test Workshop, Montreux, Switzerland, pp. 15-20, June 2002.

  • S. Bhattacharya and A. Chatterjee, ``A fast process diagnosis method using diagnosis core,'' in Proc. 9th International Mixed-Signal Test Workshop, Seville, Spain, pp. 19-24, June 2003.

  • S. Bhattacharya and A. Chatterjee, ``Built-in-test of analog and RF circuits using embedded sensors,'' in Proc. 5th IEEE International Workshop on Test Resource Partitioning Workshop, Napa Valley, CA, USA, April 2004.