Published Books and Parts of Books

1. Crnic, F., Swaminathan, M., Chatterjee, A., Kim, B., and Koppolu, S., "Electrical Test of MCMs," Chapter 13 in Microelectronics Packaging Handbook, Vol 2, Edited by Tummala, R., and Rymaszewski, E., Van Nostrand Reinhold, 1996, pp. 814-872.

2. Swaminathan, M., Kim, B., and Chatterjee, A., "A Survey of Test Techniques for MCM Substrates," Chapter 3 in Multichip Module Test Strategies, Edited by Zorian, Y., Kluwer Academic Publishers, 1997, pp. 27-38.

3. Choi, K. W., Dhillon, Y. S., Diril, U., Chatterjee, A., et. al., "Power-Performance Trade-Offs in Second Level Memory Used by an ARM-like RISC Architecture," Chapter 11 in Power Aware Computing, Kluwer Academic Publishers, Part IV, pp. 215-228, 2002.

4. Bhattacharya, S., and Chatterjee, A., "RF Testing" Chapter 16 in System On Chip Test Architectures, Edited by Wang, L. T., et. al., Morgan Kauffman publishers, 2008, pp.747-790, ISBN: 978-0-12-373973-5.

5. Bhattacharya, S., and Chatterjee, A., "RF Testing", Chapter12.7 in VLSI Test Principles and Architectures, Edited by Wang, L. T., et. al., Morgan Kauffman publishers, 2008, pp.728-736, ISBN-13: 978-0-12-370597-6.

6. Akbay, S.S., Bhattacharya, S., Keezer, D., Chatterjee, A., "Electrical Test of System on Package Technologies," Chapter 13 in Introduction to System on Package, McGraw-Hill, 2007 (to appear).

Refereed Journal Publications

7. Chatterjee, A. and Abraham, J. A., "On the C-Testability of Generalized Counters," IEEE Transactions on Computer-Aided Design, Vol. 6, No. 5, pp. 713-726, September 1987.

8. Chatterjee, A. and Abraham, J. A., "The Testability of Generalized Counters Under Multiple Faulty Cells," IEEE Transactions on Computers, Vol. 39, No. 11, pp. 1378-1385, November 1990.

9. Chatterjee, A. and Abraham, J. A., "Test Generation, Design for Testability, and Built-In Self-Test of Arithmetic Units Based on Graph Labeling," Journal of Electronic Testing: Theory and Applications, Vol. 2, pp. 351-372, 1991.

10. Hartley, R., Welles, K., Hartman, M., Chatterjee, A., Delano, P., Molnar, B., and Rafferty, C., "A Rapid Prototyping Environment for Digital Signal Processors," IEEE Design and Test of Computers, Vol. 8, No. 2, pp. 11-25, June 1991.

11. Chatterjee, A., Roy, R. K., Abraham, J. A., and Patel, J. H., "Efficient Testing Strategies for Bit and Digit-Serial Arrays Used in Digital Signal Processors," Digital Signal Processing Journal, Academic Press, Vol. 1, No. 4, pp. 231-244, October 1991.

12. Chatterjee, A. and Abraham, J. A., "Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model," IEEE Transactions on Computers, Vol. 40, No. 10, pp. 1133- 1148, October 1991.

13. Chatterjee, A., "Concurrent Error Detection and Fault-Tolerance in Linear Analog Circuits Using Continuous Checksums," IEEE Transactions on VLSI, Vol. 1, No. 2, pp. 138-150, June 1993.

14. Chatterjee, A. and d'Abreu, M. A., "The Design of Fault Tolerant Linear Digital State Variable Systems: Theory and Practice," IEEE Transactions on Computers, Vol. 42, No. 7, pp. 794-808, July 1993.

15. Chatterjee, A. and d'Abreu, M. A., "Greedy Hardware Optimization for Linear Digital Circuits Using Number Splitting and Refactorization," IEEE Transactions on VLSI, Vol. 1, No. 4, pp. 423-431, December 1993.

16. Nagi, N., Chatterjee, A., and Abraham, J. A., "Fault Simulation of Linear Analog Circuits," Analog Integrated Circuits and Signal Processing Journal, Special Issue on Analog Design- for-Test, Kluwer Academic Publishers, Vol. 4, pp. 245-260, December 1993. Also in Journal of Electronic Testing: Theory and Applications, Vol. 4, pp. 345-360, December 1993.

17. Chatterjee, A., Kim, B., and Nagi, N., "DC built-in self-test for linear analog circuits," IEEE Design and Test of Computers, Vol. 13, No.2, pp. 26-33, Summer 1996.

18. Balivada, A., Zheng, H., Nagi, N., Chatterjee, A., and Abraham, J. A., "A Unified Approach for Fault Simulation of Linear Mixed-Signal Circuits," Journal of Electronic Testing: Theory and Applications, Vol. 9, pp. 29-41, December 1996.

19. Swaminathan, M., Chatterjee, A., and Kim, B., "Testing High Density Substrates," Advanced Packaging, January 1997, pp. 33-35.

20. Kim, B., Swaminathan, M., Chatterjee, A., and Schimmel D., "A Novel Test Technique for MCM Substrates," IEEE Transactions on Components and Packaging Technology, Part B: Advanced Packaging, Vol. 20, No. 1, pp. 2-12, February 1997.

21. Swaminathan, M., Kim, B., and Chatterjee, A., "A Survey of Test Techniques for MCM Substrates," Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 10, No. 1/2, pp. 27-38, February/April 1997.

22. Chatterjee, A. and Roy, R. K., "Concurrent Error Detection in Non-linear Digital Circuits Using Time-Freeze Linearization," IEEE Transactions on Computers, Vol. 46, No. 11, pp. 1208-1218, December 1997.

23. Nguyen, H. T., Chatterjee, A., and Roy, R. K., "Activity Measures for Fast Relative Power Estimation Directed Numerical Transformations for Low Power DSP Synthesis," Journal of VLSI Signal Processing Systems, Special Issue on Systematic Trade-off Analysis in Signal Processing Systems Design, Vol. 18, No. 1, pp. 25-38, January 1998.

24. Nagi, N., Chatterjee, A., and Abraham, J. A., "Signature Analysis for Analog and Mixed- Signal Circuit Test Response Compaction," IEEE Transactions on Computer-Aided Design, Vol. 17, No. 6, pp. 540-545, June 1998.

25. Pant, P., De, V., and Chatterjee, A.,"A Novel Approach to Power Minimization in Digital Random Logic Networks," IEEE Transactions on VLSI Systems, Special Issue on Low- Power Circuit Design, Vol. 6, No. 4, pp. 538-545, December 1998.

26. Sasidhar, K., Alkalai, L., and Chatterjee, A., "Testing NASA's 3-D stack MCM Space Flight Computer," IEEE Design and Test of Computers, Vol. 15, No. 3, pp. 538-545, December 1998.

27. Nguyen, H., Roy, R. K., and Chatterjee, A., "Partial Reset Methodology and Experiments for Improving Random Pattern Testability and BIST of Sequential Circuits," Journal of Electronic Testing: Theory and Applications, Vol. 14, No. 3, pp. 259-272, June 1999.

28. Sasidhar, K., Chatterjee, A., Agarwal, V.K., and Hughes, J. L. A., "Distributed Diagnosis of Identical Units in Regular Systems," IEEE Transactions on Parallel and Distributed Systems, submitted November 1997, Letter of final acceptance received January 1999.

29. Pendurkar, R., Tovey, C., and Chatterjee, A., "Single Probe Traversal Optimzation for Efficient Testing of MCM Substrate Interconnections," IEEE Transactions on Computer- Aided Design, Vol. 18, No. 8, pp. 1178-1191, August 1999.

30. Yoon, H., Hou, J., Bhattacharya, S., Chatterjee, A., and Swaminathan, M., "Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives," Journal of VLSI Signal Processing Systems, Vol. 21., No. 3, pp. 265-276, July 1999.

31. Variyam, P. and Chatterjee, A., "Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling," IEEE Design and Test of Computers, Vol. 17, No. 3, pp. 106-115, July-September 2000.

32. Nguyen, H. and Chatterjee, A., "Number-Splitting with Shift-and-Add Decomposition for Power and Hardware Optimization in Linear DSP Synthesis," IEEE Transactions on VLSI Systems, Vol. 8., No. 3, pp. 419-424, August 2000.

33. Pant, P., Roy, R. K. and Chatterjee, A., "Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits," IEEE Transactions on VLSI Systems, Vol. 9, No. 2 , pp. 390-394, April 2001.

34. Pant, P., Hsu, Y. C., Gupta, S. K., and Chatterjee, A., "Path Delay Fault Diagnosis in Combinational Circuits with Implicit Path Enumeration," IEEE Transactions on Computer-Aided Design, Vol. 20, No. 10, pp.1226-1235, October 2001.

35. Sasidhar, K. and Chatterjee, A., "Hierarchical Diagnosis of Identical Units in a Systems," IEEE Transactions on Computers, Vol. 50, No. 2, pp. 186-191, February 2001.

36. Variyam, P. and Chatterjee, A., "Specification Driven Test Generation for Analog Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 10, October 2000, pp. 1189-1201.

37. Sasidhar, K., Chatterjee, A., and Zorian, Y., "Boundary Scan Based Relay Propagation Test of Iterative Arrays of Identical Units," IEEE Transactions on Computers, Vol. 50, No. 10, October 2001, pp. 1007-1019.

38. Pendurkar, R., Chatterjee, A., and Zorian, Y., "Switching Activity Generation with Automated BIST synthesis for Performance Testing of Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.20, No. 9, pp. 1143-1158, September 2001.

39. Variyam, P., Cherubal, S., and Chatterjee, A., "Prediction of Analog Performance Parameters Using Fast Transient Testing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vo. 21, No. 2, pp. 349-361, March 2002.

40. Cherubal, S. and Chatterjee, A., "Optimal Linearity Testing of A/D Converters," IEEE Transactions on Circuits and Systems-I, Fundamental Theory and Applications, Vol. 50, No.3, pp. 317-327, March 2003.

41. Hou, J. and Chatterjee, A., "Concurrent Transient Fault Simulator for Analog Circuits," IEEE Transactions on Computer-Aided Design, pp. 819-829, October 2003

42. Bhattacharya, S. and Chatterjee, A., "Wafer-Probe and Assembled-Package Test Co-Optimization to Minimize Overall Test Cost," ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 2, pp. 302-329, 2003.

43. Pendurkar, R. and Chatterjee, A., "A Distributed BIST for Performance Testing of MCM Interconnections, Journal of Electronic Testing: Theory and Applications, Vol 20, pp. 291-307, 2004.

44. Akbay, S., Halder, A., Chatterjee, A. and Keezer, D., "Low Cost Test of Embedded RF/Analog/Mixed-Signal Circuits in SoPs," IEEE Transactions on Advanced Packaging, Vol. 27, pp. 352-363, May 2004.

45. Seo, C. S., Chatterjee, A. and Jokerst, N., "Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems," IEICE Transactions on Fundamentals (Japan), pp. 1310-1317, November 2004.

46. Srinivasan, G., Bhattacharya, S., Cherubal, S. and Chatterjee, A., "Fast Specification Test of TDMA Power Amplifiers Using Transient Current Measurements," IEE Proceedings on Computers and Digital Techniques, Special Issue on Best Technical Contributions to DATE 2004, Vol. 152, Issue 9, pp. 632-642, September 2005.

47. Bhattacharya, S., Halder, A., Srinivasan, G. and Chatterjee, A., "Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of Systems Specifications," Journal of Electronic Testing: Theory and Applications, Vol. 21, No. 3, pp. 323-339. 2005.

48. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., "Pseudo Dual Supply Voltage Domino Logic Design," Journal of Low Power Electronics, Vol.1, pp. 145- 152, 2005.

49. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., "Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages," IEEE Transactions on VLSI, vol.13, no.9 pp. 1103- 1107, September 2005.

50. Bhattacharya, S., Senguttuvan, R. and Chatterjee, A., "Production Test Technique for Measuring BER of Ultra-Wide Band (UWB) Devices," IEEE Transactions on Microwave Theory and Techniques, IMS Special Issue, Vol. 53, No. 11, pp. 3474-3481, 2005.

51. Halder, A. and Chatterjee, A., "Test Generation for Specification Test of Analog Circuits Using Efficient Test Response Observation Methods," Microelectronics Journal, Vol. 36, No. 9, September 2005, pp. 820-832.

52. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., " Analysis and Optimization of Nanometer CMOS Circuits for Soft-error Tolerance," IEEE Transactions on VLSI, Vol. 15, No. 5, May 2006, pp. 514-524.

53. Xuan, X., Singh, A. D. and Chatterjee A., "Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects," Journal of Electronic Testing, Theory and Applications, Vol. 22, Nos 4-6, December 2006, pp. 471-482.

54. Bhattacharya, S.; Chatterjee, A., "A DFT Approach for Testing Embedded Systems Using DC Sensors," IEEE Design & Test of Computers, Vol. 23, No. 6, June 2006, pp. 464 - 475.

55. Bhattacharya, S.; Nair, S.; Chatterjee, A., "An Accurate DNA Sensing and Diagnosis Methodology Using Fabricated Silicon Nanopores," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 53, No. 11, Nov. 2006, pp. 2377 - 2383.

56. Goyal, S., Chatterjee, A. and Purtell M., "A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters," Journal of Electronic Testing, Theory and Applications, Vol. 23, No. 1, Feb. 2007, pp. 95-106.

57. Voorakaranam, R., Akbay, S.S., Bhattacharya, S., Cherubal, S. and Chatterjee, A, "Signature Testing of Analog and RF Circuits: Algorithms and Methodology," IEEE Transactions on Circuits and Systems, Vol 54, Issue 5, May 2007, pp. 1018-1031.

58. Y. S. Dhillon, A. U. Diril, Chatterjee, A., "Delay-Assignment-Variation (DAV) Based Optimization of Digital CMOS Circuits for Low Power Consumption," Journal of Low Power Electronics , Vol. 3, 2007, pp. 78-95.

59. Han, D., Bhattacharya, S., and Chatterjee, A., "Low-Cost Parametric Test and Diagnosis of RF Systems Using Multi-Tone Response Envelope Detection," IET Proceedings on Computers & Digital Techniques, Vol. 1, Issue 3, May 2007, pp. 170-179.

60. Senguttuvan, R., Bhattacharya, S., and Chatterjee, A., "Test Method for Measuring Bit Error Rate of Pulsed Transceivers in Presence of Narrowband Interferers", IEEE Transactions on Microwave Theory and Techniques, Vol. 55, Issue 9, September 2007, pp. 1942 - 1950.

61. Datta, R., Abraham, J. A, Diril, U and Chatterjee, A., " Performance Optimized Design for Parametric Reliability, Journal of Electronic Testing, Theory and Applications, Springer, Netherlands, DOI 10.1007/s10836-007-5001-y, Vol. 24, No. 3, June 2008, pp. 129-141.

62. Halder, A.,Bhattacharya S. and Chatterjee, A., "System-Level Specification Testing of Wireless Transceivers," IEEE Transactions of VLSI , Vol 16, Issue 3, March 2008, pp. 263-276.

63. Srinivasan, G., Tanezler, F. and Chatterjee, A., "Efficient Loopback Test of Frequency Modulated RF Systems," IEEE Design and Test of Computers, April 2008, Vol. 25, Issue 2,, DOI 10.1109/MDT.2008.46, pp. 150-159.
.

Submitted for publication:

64. Srinivasan, G., Bhattacharya, S., Cherubal, S. and Chatterjee, A., "High-Quality MTPR Production Test of ADSL Devices on Low-cost ATE," IEEE Transactions on VLSI., (submitted 2007).

65. Senguttuvan, R., Bhattacharya, S., Chatterjee, A., "Low Cost EVM Test of Wireless OFDM Devices", IEEE Transactions on VLSI (Submitted Jun 2006, Revised November 2007).

66. Senguttuvan, R., Sen. S., Chatterjee, A.," Multi-Dimensional Adaptive Power Management for Low-Power Operation of Wireless Devices", IEEE Transactions on Circuits and Systems, (Submitted Aug 2007, Revised January 2008).

67. Natarajan, V., Senguttuvan, R., Sen, S., Chatterjee, A., "Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems", VLSI Design Journal, (Submitted October 2007, Revised February 2008).

68. Goyal, S. and Chatterjee, A., "Linearity Testing of A/D Converters Using Selective Code Measurement," Journal of Electronic Testing: Theory and Applications (Submitted November 2007).

69. Ashouei, M., Chatterjee, A. and Singh, A. D., "Fast Accurate Estimation of Correlated Within Die Variability in Dual-Vt CMOS Circuits and its Impact on Variability Aware Layout," IEEE Transactions on VLSI, submitted July 2007.

70. Ashouei, M. and Chatterjee, A., "Probabilistic Error Compensation in Linear Digital Systems," IEEE Transactions on VLSI, submitted June 2007, Revised January 2008).

71. Ashouei, M. Chatterjee, A. and Singh, A. D., "Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic," IEEE Transactions on VLSI, submitted June 2007).

72. Srinivasan, G., Taenzler, F. and Chatterjee, A., "On-the-Fly Seamless Diagnosis of Multi-Port Complex S-Parameters of RF Loadboards During High Volume IC Production," IEEE Transactions on Instrumentation and Measurement, (Submitted Jan 2007).

Conference Papers

73. Chatterjee, A., Chang, T., Molnar, K., and Jerdonek, R., "WIRE: An Interactive Tool for VLSI Chip Routing," Proceedings, International Conference on Computer Design, Portchester, NY, October 1985, pp. 575-578.

74. Chatterjee, A. and Abraham, J. A., "C-Testability of Generalized Tree Structures with Applications to Wallace Trees and Other Circuits," Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, November 1986, pp. 288-291.

75. Chatterjee, A. and Abraham, J. A., "Test Generation for Arithmetic Units by Graph Labeling," Proceedings, 17th International Symposium on Fault Tolerant Computing, Pittsburgh, PA, July 1987, pp. 284-289.

76. Chatterjee, A. and Abraham, J. A., "New Results on the Testability of Generalized Counters," Proceedings, International Symposium on Electronic Devices, Circuits and Systems, I.I.T. Kharagpur, India, December 1987, pp. 624-626.

77. Abraham, J. A., Brahme, D. S., Chandra, S. J., Chatterjee, A., and Patel, J. H., "Speedup of Test Generation Through the Use of High Level Knowledge," Techcon 88, Dallas, TX, October 1988, pp. 145-148.

78. Chatterjee, A. and Abraham, J. A., "NCUBE: An Automatic Test Generation Program for Iterative Logic Arrays," Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, November 1988, pp. 428-431.

79. Hartley, R., Welles, K., Hartman, M., Delano, P., and Chatterjee, A., "Rapid Prototyping Using High Density Interconnects," Proceedings, European Design Automation Conference, Edinburgh, Scotland, U.K., March 1990, pp. 439-443.

80. Welles, K., Hartley, R., Chatterjee, A., Delano, P., and Hartman, M., "A Testing Methodology for Large Scale Hybrid VLSI," Proceedings, International Symposium on Circuits and Systems, New Orleans, LA, May 1990, pp. 2724-2727.

81. Chatterjee, A. and Abraham, J. A., "Test Generation for Hybrid Iterative Logic Arrays," Proceedings, International Symposium on Circuits and Systems, New Orleans, LA, May 1990, pp. 17-20.

82. Roy, K., Chatterjee, A., and Abraham, J. A., "Issues in Synthesis for Delay and Bridging Faults," Proceedings, International Symposium on Circuits and Systems, New Orleans, LA, May 1990, pp. 3101-3104.

83. Chatterjee, A. and Hartley, R., "A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing," Proceedings, Design Automation Conference, Orlando, FL, June 1990, pp. 36-39.

84. Chatterjee, A., Roy, R. K., Abraham, J. A., and Patel, J. H., "Efficient Testing Strategies for Bit and Digit-Serial Arrays," Fourth CSI/IEEE International Symposium on VLSI Design, New Delhi, India, January 1991, pp. 142-147.

85. Chatterjee, A. and d'Abreu, M. A., "Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems," Proceedings, 21st Fault Tolerant Computing Symposium, Montreal, Canada, July 1991, pp. 136-143.

86. Chatterjee, A. and d'Abreu, M. A., "Syndrome Based Functional Delay Fault Location in Linear Digital Data Flow Graphs," Proceedings, International Conference on Computer Design, Boston, MA, September 1991, pp. 212-215.

87. Chatterjee, A., "Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums," Proceedings, International Test Conference, Nashville, TN, September 1991, pp. 582-591.

88. Chatterjee, A., "Checksum Based Concurrent Error Detection in Linear Analog Systems with Second and Higher Order Stages," Proceedings, 10th IEEE VLSI Test Symposium, Atlantic City, NJ, April 1992, pp. 286-291.

89. Roy, R. K., Nagi, N., Chatterjee, A., and d'Abreu, M. A., "Delay Fault Testing of Iterative Arithmetic Arrays," Proceedings, 10th IEEE VLSI Test Symposium, Atlantic City, NJ, April 1992, pp. 25-30.

90. Roy, R. K., Chatterjee, A., Patel, J. H., Abraham, J. A., and d'Abreu, M. A., "Automatic Test Generation for Linear Digital Systems With Bi-level Search Using Matrix Transform Methods," Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, October 1992, pp. 224-228.

91. Nagi, N., Chatterjee, A., and Abraham, J. A., "MIXER: Mixed-Signal Fault Simulator," Proceedings, International Conference on Computer Design, Boston, MA, October 1992, pp. 568-571.

92. Chatterjee, A., "A New Approach to Fault Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations," Proceedings, International Conference on Computer Design, Boston, MA, November 1992, pp. 478-481.

93. Chatterjee, A., Roy, R. K., and d'Abreu, M. A., "Greedy Hardware Optimization for Linear Digital Systems Based on Real-Number Splitting and Repeated Factorization," Proceedings, IEEE International Conference on VLSI Design, Bombay, India, January 1993, pp. 154-159.

94. Chatterjee, A. and Roy, R. K., "An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition," Proceedings, Design Automation Conference, Dallas, TX, June 1993, pp. 343-348.

95. Chatterjee, A. and Roy, R. K., "Concurrent Error Detection Schemes for Non-linear Digital Circuits With Applications to Adaptive Filters," Proceedings, International Conference on Computer Design, Boston, MA, October 1993, pp. 606-609.

96. Nagi, N., Chatterjee, A., and Abraham, J. A., "FAST: Fault-Based Automatic Simulation Assisted Test Generator for Linear Analog Circuits," Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, November 1993, pp. 88-91.

97. Chatterjee, A. and Roy, R. K., "Synthesis of Low-Power Linear DSP Circuits Using Activity Metrics," Proceedings, IEEE International Conference on VLSI Design, New Delhi, India, January 1994, pp. 265-270.

98. Chatterjee, A. and Roy, R. K., "Design for Diagnosability in Linear Digital Filters Using Time-Space Expansion," Proceedings, 12th IEEE VLSI Test Symposium, April 1994, pp. 48- 53.

99. Nagi, N., Chatterjee, A., Balivada, A., and Abraham, J. A., "Signature Analyzer for Analog and Mixed-Signal Circuits," Proceedings, International Conference on Computer Design, Boston, MA, October 1994, pp. 568-571.

100. Chatterjee, A. and Abraham, J. A., "RAFT: A Program for Rapid-Fire Test of Digital Circuits for Marginal Delays and Delay Faults," Proceedings, International Conference on Computer- Aided Design, Santa Clara, CA, October 1994, pp. 340-343.

101. Nagi, N., Chatterjee, A., Balivada, A., and Abraham, J. A., "Efficient Multisine Testing of Analog Circuits," Proceedings, International Conference on VLSI Design, New Delhi, India, January 1995, pp. 234-238.

102. Nguyen, H. T. and Chatterjee, A., "OPTIMUS: A New Program for Hardware Optimization Using Number-Splitting and Shift-and-Add Decomposition," Proceedings, Advanced Research on VLSI, Chapel Hill, NC, April 1995, pp. 256-271.

103. Roy, K., Roy, R. K., and Chatterjee, A., "Stress Testing of Combinational VLSI Circuits Using Existing Test Sets," Proceedings, IEEE International Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1995, pp. 93-98.

104. Kim, B., Chatterjee, A., and Swaminathan, M., "A Novel Low-Cost Approach to MCM Interconnect Test," Proceedings, International Test Conference, Washington, DC, October 1995, pp. 184-192.

105. Sasidhar, K., Chatterjee, A., Agarwal, V. K., and Hughes, J. L. A., "Distributed Probabilistic Diagnosis of MCMs on Large Area Substrates," Proceedings, International Test Conference, Washington DC, October 1995, pp. 208-216.

106. Kim, B., Swaminathan, M., and Chatterjee, A., "A Novel MCM Interconnect Test Technique Based on Resonator Principles and Transmission Line Theory," IEEE 4th Topical Meeting On Electrical Performance of Electrical Packaging, Portland, OR, October 1995, pp. 117- 119.

107. Chatterjee, A., Kim, B., and Nagi, N., "Low-Cost DC Built-In Self-Test of Linear Analog Circuits Using Checksums," Proceedings, 9th International Conference on VLSI Design, Bangalore, India, January 1996, pp. 230-233.

108. Sasidhar, K. and Chatterjee, A., "Hierarchical Probabilistic Diagnosis of MCMs on Large Area Substrates," Proceedings, 9th International Conference on VLSI Design, Bangalore, India, January 1996, pp. 65-68.

109. Kim, B., Swaminathan, M., and Chatterjee, A., "Electrical Interconnect Test Technique for MCMs," 1st International Conference on Emerging Microelectronics and Interconnection Technologies, Bangalore, India, February 1996, pp. 285-290.

110. Sasidhar, K., Chatterjee, A., and Zorian, Y., "Relay Propagation Scheme for Testing of MCMs on Large Area Substrates," Proceedings, European Test Conference, Paris, France, March 1996, pp. 131-135.

111. Kim, B., Chatterjee, A., and Swaminathan, M., "Low Cost Diagnosis of Defects in MCM Substrate Interconnections," Proceedings, VLSI Test Symposium, Princeton, NJ, April 1996, pp. 260-265.

112. Chatterjee, A., Jayabharathi, R., Pant, P., and Abraham, J. A., "Nonrobust Tests for Stuck Fault Detection Using Signal Waveform Analysis: Feasibility and Advantages," Proceedings, VLSI Test Symposium, Princeton, NJ, April 1996, pp. 354-359.

113. Kim, B., Swaminathan, M., and Chatterjee, A., "High Resolution and Low Cost Test Technique for Unpopulated MCM Substrates," 46th Electronics Components and Technology Conference, Orlando, FL, May 1996, pp. 226-233.

114. Nguyen, H. T. and Chatterjee, A., "Activity Measures for Fast Relative Power Estimation Directed Numerical Transformations for Low Power DSP Synthesis," Proceedings, International Symposium on Circuits and Systems, Atlanta, GA, May 1996, pp. 17-21.

115. Sasidhar, K., Chatterjee, A., and Zorian, Y., "Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates," Proceedings, International Test Conference, October 1996, pp. 818-827.

116. Sasidhar, K., Kim, B., Chatterjee, A., and Swaminathan, M., "Low Cost Parallel MCM Interconnect Test On Large Area Substrates," Proceedings, ISHM Conference, October 1996, pp. 218-223.

117. Pendurkar, R., Chatterjee, A., and Tovey, C., "Optimal Single Probe Traversal Algorithm for Testing of MCM Substrates," Proceedings, International Conference on Computer Design, October 1996, pp. 396-401.

118. Nguyen, H. T., Roy, R. K., and Chatterjee, A., "Impact of Partial Reset on Fault Independent Testing and BIST," Proceedings, International Conference on VLSI Design, Hyderabad, India, January 1997, pp. 537-539.

119. Variyam, P. and Chatterjee, A., "FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representations," Proceedings, 10th International Conference on VLSI Design, January 1997, pp. 408-412.

120. Yoon, H., Chatterjee, A., and Hughes, J.L.A., "Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits," Proceedings, 10th International Conference on VLSI Design, January 1997, pp. 393-397.

121. Chatterjee, A. and Nagi, N., "Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial," Proceedings, 10th International Conference on VLSI Design, January 1997, pp. 388-392.

122. Sasidhar, K., Alkalai, L., and Chatterjee, A., "Test Strategies for a 3D Stack Multichip Module Space Flight Computer," Proceedings, ISHM MCM Conference, March 1997, pp. 181-186.

123. Sasidhar K., Chatterjee, A., and Swaminathan, M., "Low Cost Test of MCMs Using Testable Die Carriers," IEEE MCM Conference, 1997, pp. 138-143.

124. Variyam, P., Chatterjee, A., and Nagi, N., "Low Cost and Efficient Digital-Compatible BIST for Analog Circuits Using Pulse Response Sampling," Proceedings, 15th IEEE VLSI Test Symposium, April 1997, pp. 261-266.

125. Pant, P., De, V., and Chatterjee, A., "Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks," Proceedings, Design Automation Conference, June 1997, pp. 403-408.

126. Kao, W., Voorakaranam, R., and Chatterjee, A., "AHDL-Based Analog Behavioral Fault Modeling and Simulation," Proceedings, Analog and Mixed-Signal Applications Conference, July 1997, pp. 93-96.

127. Variyam, P. and Chatterjee, A., "Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient Response Sampling," Proceedings, International Conference on Computer-Aided Design, November 1997, pp. 382-385.

128. Voorakaranam, R., Chakrabarti, S., Hou, J., Gomes, A., Cherubal, S., Chatterjee, A., and Kao, W., "Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis," Proceedings, International Test Conference, November 1997, pp. 903-912.

129. Nguyen, H. T., Roy, R. K., and Chatterjee, A., "Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits," Proceedings, International Conference on VLSI Design, January 1998, pp. 199-204.

130. Yoon, H., Variyam, P., Chatterjee, A., and Nagi, N., "Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits," Proceedings, VLSI Test Symposium, April 1998, pp. 145-150.

131. Variyam, P. and Chatterjee, A., "Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements," Proceedings, VLSI Test Symposium, April 1998, pp. 132-137.

132. Gomes, A., Voorakaranam, R., and Chatterjee, A., "Modular Fault Simulation of Mixed- Signal Circuits with Fault Ranking by Severity," Symposium on Defect and Fault Tolerance in VLSI, September 1998, pp. 341-348.

133. Variyam, P. and Chatterjee, A., "Genetic Test Stimulus Optimization for Analog Circuits," Symposium on Defect and Fault Tolerance in VLSI, September 1998, pp. 335-340.

134. Yoon, H., Hou, J., Chatterjee, A., and Swaminathan, M., "Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives," Proceedings, International Conference on Computer Design, October 1998, pp. 588-593.

135. Pendurkar, R., Chatterjee, A., and Zorian, Y., "A Distributed BIST Technique for Diagnosis of MCM Interconnections," Proceedings, International Test Conference, October 1998, pp. 214-221.

136. Kim, B., Chatterjee, A., and Keezer, D., "High Throughput Testing of MCM Substrates," Proceedings, International Test Conference, October 1998.

137. Hou, J. and Chatterjee, A., "CONCERT: A Concurrent Transient Fault Simulator for Nonlinear Analog Circuits," IEEE International Conference on Computer-Aided Design, November 1998, pp. 384-391.

138. Pendurkar, R., Chatterjee, A., and Zorian, Y., "Synthesis of BIST Hardware for Performance Testing of MCM Interconnections," IEEE International Conference on Computer-Aided Design, November 1998, pp. 69-73.

139. Chakrabarti, S. and Chatterjee, A., "Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models," International VLSI Design Conference, January 1999, pp. 518- 523.

140. Variyam, P., Hou, J., and Chatterjee, A., "DC Test Generation for Analog Circuits Using Partial Numerical Simulation," International VLSI Design Conference, January 1999, pp. 597-602.

141. Chakrabarti, S., Cherubal. S., and Chatterjee, A., "Fault Diagnosis of Mixed-Signal Electronic Systems," IEEE Aerospace Conference, Vol. 3, March 1999, pp. 169-179.

142. Chakrabarti, S., and Chatterjee, A., "Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits," The Twentieth Anniversary Conference on Advanced Research in VLSI, March 1999, pp. 327-341.

143. Voorakaranam, R., and Chatterjee, A., "Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test," The Twentieth Anniversary Conference on Advanced Research in VLSI, March 1999, pp. 342-355.

144. Cherubal, S., and Chatterjee, A., "Parametric Fault Diagnosis for Analog Systems Using Functional Mapping," Design, Automation and Test in Europe, March 1999, pp. 195-200.

145. Variyam, P., Hou, J., and Chatterjee, A., "Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation," VLSI Test Symposium, April 1999, pp. 214-219.

146. Voorakaranam, R. and Chatterjee, A., "Hierarchical Test Generation for Analog Circuits Using Incremental Test Development," Proceedings, VLSI Test Symposium, April 1999, pp. 296-301.

147. Chakrabarti, S. and Chatterjee, A., "Fault Modeling and Fault Sampling for Isolating Faults in Analog and Mixed-Signal Circuits," International Symposium on Circuits and Systems, Vol. 2, June 1999, pp. 444-447.

148. Hou, J., Kao, W., and Chatterjee, A., "A Novel Concurrent Fault Simulation Method for Mixed-Signal Circuits," International Symposium on Circuits and Systems, June 1999, pp. 2.448-2.451.

149. Pant, P., Roy, R. K., and Chatterjee, A., "Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits," Proceedings, Midwest Symposium on Circuits and Systems, August 1999.

150. Cherubal. S. and Chatterjee, A., "A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms," Proceedings, International Symposium on Defect and Fault Tolerance in VLSI, 1999, pp. 357-365.

151. Chakrabarti, S. and Chatterjee, A., "On-Line Fault Detection in DSP Circuits Using Extrapolated Checksums with Minimal Test Points," Proceedings, International Test Conference, November 1999.

152. Pant, P. and Chatterjee, A., "Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits," Proceedings, International Conference on Computer-Aided Design, November 1999.

153. Cherubal, S. and Chatterjee, A., "An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards," Proceedings, Thirteenth International Conference on VLSI Design, January 2000, pp.550-555.

154. Voorakaranam, R., Hou, J., Variyam, P., Chakrabarti, S., Cherubal, S., Gomes, A., and Chatterjee, A., "Low Cost Test and Diagnosis of Mixed-Signal Modules," SEMICON Korea Technical Symposium, February 2000, pp. 247-254.

155. Cherubal, S. and Chatterjee, A., "Test Generation Based Diagnosis of Device Parameters for Analog Circuits," Proceedings, Design Automation and Test in Europe, March 2000, pp. 596-602.

156. Voorakaranam, R. and Chatterjee, A., "Test Generation for Accurate Prediction of Analog Specifications," Proceedings, VLSI Test Symposium, April 2000, pp. 137-142.

157. Variyam, P. N., Cherubal, S., and Chatterjee, A., "Fast Transient Testing of Analog ICs: An Industrial Experience," Proceedings, TECHCON, June 2000.

158. Voorakaranam, R. and Chatterjee, A., "Low Cost Jitter Measurement for Phase Locked Loops, Proceedings, TECHCON, June 2000.

159. Hou, J. and Chatterjee, A., "Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping," Proceedings, IEEE International Conference on Computer Design, October 2000, pp. 35-41.

160. Chakrabarti, S. and Chatterjee, A., "Partial Simulation Driven Test Generation for Analog Circuits," Proceedings, IEEE International Conference on Computer-Aided Design, October 2000.

161. Cherubal, S. and Chatterjee, A., "Optimal INL/DNL Testing of A/D Converters Using a Linear Model," Proceedings, International Test Conference, October 2000, pp. 358-366.

162. Voorakaranam, R. and Chatterjee, A., "Low Cost Jitter Measurement Technique for Phase Locked Loops," Proceedings, Midwest Symposium on Circuits and Systems, November 2000.

163. Pant, P. and Chatterjee, A., "Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Testing, Proceedings, International Test Conference, October 2000.

164. Cherubal, S. and Chatterjee, A., "Test Generation for Fault Isolation in Analog Circuits Using Behavioral Models," Proceedings, Asian Test Symposium, December 2000, pp. 19-24.

165. Xuan, X. and Chatterjee, A., "Sensitivity and Reliability Evaluation for Mixed-Signal ICs Under Electromigration and Hot-Carrier Effects," Proceedings, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 323-329.

166. Choi, K. W. and Chatterjee, A., "Efficient Instruction-Level Optimization Methodology for Low Power Embedded Systems," Proceedings, ACM/IEEE International Symposium on System Synthesis, September 2001, pp. 215-228.

167. Cherubal, S. and Chatterjee, A., "A High Resolution Jitter Measurement Technique Using ADC Sampling," Proceedings, International Test Conference, November 2001, pp. 838-847.

168. Sahu, B. and Chatterjee, A., "Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models," Proceedings, Asian Test Symposium, November 2001, pp. 405-410.

169. Gomes, A. and Chatterjee, A., "Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator," Proceedings, Asian Test Symposium, November 2001, pp. 411-416.

170. Halder, A. and Chatterjee A., "Specification Based Digital Compatible Built-In Test of Embedded Analog Circuits," Proceedings, Asian Test Symposium, November 2001, pp. 344-349.

171. Voorakaranam, R., Cherubal, S., and Chatterjee, A., "A Signature Test Framework for Rapid Production Testing of RF Circuits," Proceedings, Design Automation and Test in Europe, March 2002.

172. Halder, A. and Chatterjee, A., "Measuring Stray Capacitance on Tester Hardware," Proceedings, VLSI Test Symposium, April 2002, pp. 351-356.

173. Choi, K. W. and Chatterjee, A., "HA2TSD: Hierarchical time slack distribution for ultra-low power CMOS VLSI," Proc. of the International Symposium on Low Power Electronics and Design, Sept. 2002, pp. 207-212.

174. Puttaswami, K., Choi, K. W., Chatterjee, A., et. al., "System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory," Proc. of ACM/IEEE International Symposium on System Synthesis, Oct. 2002.

175. Choi, K. W. and Chatterjee, A., "PA-ZSA (Power Aware Zero Slack Algorithm): A graph based timing analysis for ultra low-power CMOS VLSI," Proc. of PATMOS' 2002, Oct. 2002, pp. 178-187.

176. Park, J. C., Choi, K. W., Chatterjee, A., et. al, "Energy minimization of a pipelined processor using a low voltage pipelined cache," Proc. of 36th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 3-6, 2002.

177. Seo, C. S. and Chatterjee, A., "A CAD Tool for System-on-Chip Placement and Routing With Free-Space Optical Interconnect," Proceedings, International Conference on Computer Design, Nurenberg, Germany, Nov 2002, pp. 24-29.

178. Diril, A. U., Dhillon, Y. S., Choi, K. W. and Chatterjee, A, "An O(N) Supply Voltage Assignment Algorithm for Low-Energy Serially Connected Data Flow Graphs, Proceedings ISVLSI, February 2003, pp.173-179.

179. Xuan, X., Singh, A. and Chatterjee A., "Reliability Evaluation for Integrated Circuit With Defective Interconnect Under Electromigration," Proceedings, International Symposium on Quality Electronic Design, March 2003, pp. 29-35.

180. Xuan, X., Chatterjee, A. and Singh, A. D., "ARET: A Tool for System-Level IC Reliability Simulation," Proceedings International Reliability Physics Symposium, March 2003, pp. 572-574.

181. Bhattacharya, S. and Chatterjee, A, "High-Coverage Analog Wafer-Probe Test Design and Co-Optimization with Assembled-Package Test to Minimize Overall Test Cost," Proceedings, VLSI Test Symposium, April 2003, pp. 89-95.

182. Seo, C. S., Chatterjee, A. and Drabik, T. A., "Wiring Optimization for Propagation Delay and Reduced Power Consumption in Multi-Chip Modules with Free-Space Optical Interconnect," Proceedings, ECTC, 2003, pp. 1-6.

183. Shin, J., Seo, C. S., Chellappa, A., Brook, M., Chatterjee, A. and Jokerst, N., "Comparison of Electrical and Optical Interconnect," Proceedings, ECTC, 2003, pp. 1067-1072.

184. Seo, C. S. and Chatterjee, A., "Optimization of Board-Level H-Tree Optical Clock Distribution," Proceedings, International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), July 2003, pp. 609-611.

185. Bhattacharya, S., Halder, A. and Chatterjee, A., "Automatic Alternate Test Generation for RF Circuits Using Behavioral Models," Proceedings, TECHCON, Dallas, TX, August 2003.

186. Choi, K.W. and Chatterjee, A, "UDSM (ultra deep submicron)-Aware Post-Layout Device and Interconnect Co-optimization for Ultra Low-Power CMOS VLSI," Proceedings, ISLPED, Aug. 25-27, 2003, pp. 72-78.

187. Halder, A., Bhattacharya, S. and Chatterjee, A., "Automatic Multitone Alternate Test Generation for RF Circuits Using Behavioral Models," Proceedings, International Test Conference, Charlotte, NC, September 2003, pp. 665-673.

188. Voorakaranam, R., Newby, R., Cherubal, S., Cometta, B., Kuehl, T., Majernik, D. and Chatterjee, A., "Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results," Proceedings, International Test Conference, Charlotte, NC, September 2003, pp. 1174-1181.

189. Chatterjee, A., "Seamless Research Between Academia and Industry to Facilitate Test of Integrated High-Speed Wireless Systems: Is this an Illusion ?," Proceedings, International Test Conference, Panel: RF Test 101: Defining the Problem and Finding Solutions, Charlotte, NC, September 2003.

190. Dhillon, Y. S., Diril, U. and Chatterjee, A., "Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Multiple Threshold Voltages at the Module Level," Proceedings, IEEE International Conference on Computer-Aided Design, November 2003, pp. 693-700.

191. Xuan, X., Chatterjee, A., Singh, A. D., Kim, N. P. and Chisa, M. T., "IC Reliability ARET and its Application in Design-for-Reliability," Proceedings, Asian Test Symposium, Xian, China, Vol. 12, November 2003, pp. 18-21.

192. Cherubal, S., Voorakaranam, R., Chatterjee, A., McLaughlin, J., Smith, J. L. and Majernik, D. M., "Concurrent RF Test Using Optimized Modulated RF Stimuli," Proceedings, VLSI Design Conference, Bombay, India, Jan 2004, pp. 1017-1022.

193. Srinivasan, G., Bhattacharya, S., Cherubal, S. and Chatterjee, A., "Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements," Proceedings, Design Automation and Test in Europe, Paris, France, February 2004, pp. 280-285.

194. Halder, A. and Chatterjee, A., "Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits," Proceedings, International Symposium on Quality Electronic Design, San Jose, CA, March 2004, pp. 401-406.

195. Seo, C. S., Chatterjee, A. and Drabik, T., "Optically Interconnected Intelligent RAM Multiprocessor: Gigascale Opto-IRAM," Proceedings, International Conference on Computers and Their Applications (CATA), March 2004, pp. 256-260.

196. Xuan, X., Chatterjee, A. and Singh, A. D., "Local Redesign for Reliability of CMOS Digital Circuits Under Device Degradation," International Reliability Physics Symposium (IRPS), Vol. 42, April 2004, pp. 651-652.

197. Bhattacharya, S., Srinivasan, G., Cherubal, S., Halder, A. and Chatterjee, A, "System-Level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams," Proceedings, VLSI Test Symposium, April 2004, pp. 229-234.

198. Akbay, S. and Chatterjee, A., "Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference," Proceedings, VLSI Test Symposium, April 2004, pp. 273-278.

199. Raghunathan, A., Shin, H, J., Abraham, J. and Chatterjee, A., "Prediction of Analog Performance Parameters Using Oscillation Based Test," Proceedings, VLSI Test Symposium, April 2004, pp. 377-382.

200. Seo, C. S., Chatterjee, A., Cho, S. Y. and Jokerst, N., "Design and Optimization of Board Level Optical Clock Distribution Networks for High Performance Systems-on-Package," Proceedings, Great Lakes Symposium on VLSI (GLSVLSI), April 2004, pp. 292-297.

201. Seo, C. S., Chatterjee, A. and Jokerst, N., "Physical Design of Optoelectronic Systems-on-Package Using Optoelectronic Interconnect," Proceedings, Electronic Components and Technology Conference (ECTC), June 2004, pp. 29-34.

202. Xuan, X., Singh, A. D. and Chatterjee, A., " Application of Local Design-for-Reliability Techniques for Reducing Wear-Out Degradation of CMOS Combinational Logic Circuits," Proceedings, European Test Symposium, Ajaccio, France, June 2004, pp. 24-29.

203. Xuan, X., Chatterjee, A. and Singh, A. D., "Design of Reliable CMOS Digital Circuits Using Iterative Local Reliability Improvement," Proceedings, International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw, Poland, June 2004.

204. Dhillon, Y. S., Diril, U. and Chatterjee, A., "Sizing CMOS Circuits for Increased Transient Error Tolerance," Proceedings, International On-Line Testing Symposium, Madiera, Portugal, July 2004, pp. 11-16.

205. Han, D. H. and Chatterjee, A., "Adaptive Response Surface Modeling Based Method for Analog Circuit Sizing," Proceedings, IEEE International System-on-Chip Conference, Santa Clara, CA, September 2004, pp. 109-112.

206. Bhattacharya, S. and Chatterjee, A., "Use of Embedded Sensors for Built-In Test of RF Circuits," Proceedings, International Test Conference, Charlotte, NC, October 2004, pp. 801-809.

207. Raghunathan, A., Shin, H, J., Abraham, J. and Chatterjee, A., "Quasi-Oscillation Based Test of Analog Circuits," Proceedings, International Test Conference, October 2004.

208. Dhillon, Y. S., Diril, U., Chatterjee, A. and Singh, A. D., "Low-Power Dual Vth Pseudo Dual Vdd Domino Circuits," Proceedings, 17th Symposium on Integrated Circuits and Systems Design, Porto de Galinhas, Brazil, September 2004, pp. 273-277.

209. Bhattacharya, S. and Chatterjee, A., "A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits," Proceedings, Asian Test Symposium, Kenting, Taiwan, November 2004, pp. 68-73.

210. Srinivasan, G., Goyal, S. and Chatterjee, A., "Reconfiguration for Enhanced Alternate Test," Proceedings, Asian Test Symposium, Kenting, Taiwan, November 2004, pp. 302-307.

211. Han, D. H. and Chatterjee, A., "Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost," Proceedings, Asian Test Symposium, Kenting, Taiwan, November 2004, pp. 420-425.

212. Halder, A., Bhattacharya, S., Srinivasan, G. and Chatterjee, A ,"A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode," Proceedings, VLSI Design Conference, Kolkata, India, Jan 2005, pp. 289-294 (Received Conference Best Paper Award).

213. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., "Level-shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits using Dual Threshold Voltages," Proceedings VLSI Design Conference, Kolkata, India, January 2005, pp. 159-164.

214. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., "Low-power domino circuits using NMOS pull-up on off-critical paths," Proceedings, Asia and South Pacific Design Automation Conference , Vol.1, pp. 533- 538, Jan. 2005.

215. Dhillon, Y. S., Diril, U., Chatterjee, A. and Singh, A. D., "Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits," Proceedings, Design Automation and Test in Europe, Munich, Germany, March 2005, pp. 288-293.

216. Diril, A.U., Dhillon, Y.S., Chatterjee, A. and Singh, A.D., "Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance," Proceedings, VLSI Test Symposium, May 2005, pp. 298- 303.

217. Halder, A. and Chatterjee, A., "Low-Cost EVM Test for Wireless Receiver Systems," Proceedings, VLSI Test Symposium, Palm Springs, CA, May 2005, pp. 255-260.

218. Akbay, S. and Chatterjee, A., "Built-In Test of RF Components Using Feature Extraction Sensors," Proceedings, VLSI Test Symposium, Palm Springs, CA, May 2005, pp. 243-248.

219. Bhattacharya, S. and Chatterjee, A., "Production Test Methods for Measuring Out-of-Band Interference of Ultra Wide Band Devices," Proceedings, VLSI Test Symposium, Palm Springs, CA, May 2005, pp. 137-142.

220. Seo, C. S., Chatterjee, A. and Jokerst, N., "Physical Design of Optoelectronic Systems-on-a-Package: A CAD Tools and Algorithms," Proceedings, International Symposium on Quality Electronic Design, May 2005.

221. Srinivasan, G., Cherubal, S., Variyam, P., Teklu, M., Wang, C.P., Guidry, D. and Chatterjee, A., "Accurate Measurement of Multi-Tone Power Ratio (MTPR) of ADSL Devices Using Low Cost Testers," Proceedings, European Test Symposium , May 2005, Talinn, Estonia, pp. 68-73.

222. Bhattacharya, S., Senguttuvan, R. and Chatterjee, A., "Production Test Method for Evaluating the Effect of Narrow-Band Interference on Data Errors in Ultra Wide Band (UWB) Receivers," Proceedings, IEEE MTT-S International Microwave Symposium, Long Beach, CA, June 2005, pp. 1513-1516.

223. Dhillon, Y.S., Diril, A.U., Chatterjee, A. and Metra, C., "Load and Logic Co-optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits," Proceedings, On-Line Testing Symposium, Cannes, France, July 2005, pp. 35-40.

224. Cazeaux, J. M., Rossi, D., Omana, M., Metra, C. and Chatterjee, A., "On Transistor Level Gate Sizing for Increased Robustness to Transient Faults," Proceedings, On-Line Testing Symposium, Cannes, France, July 2005, pp. 23-28.

225. Han, D., Akbay, S. S., Bhattacharya, S. and Chatterjee, A., "On-Chip Self Calibration of RF Circuits Using Specification-Driven Built-In Self Test," Proceedings, On-Line Testing Symposium, Cannes, France, July 2005, pp. 106-111.

226. Senguttuvan, R., Bhattacharya, S. and Chatterjee, A., "Design Considerations and Effect of Manufacturing Process Variations on UWB Transceiver Specifications," Proceedings, IEEE International Conference on Ultra-Wideband, Zurich, Switzerland, September 2005, pp. 553-558.

227. Bhattacharya, S., Senguttuvan, R. and Chatterjee, A., "Production test for MB-OFDM UWB Transmitters: Overview and Methods," Proceedings, TECHCON, October 2005.

228. Srinivasan, G., Chatterjee, A., Cherubal, S. and Variyam, P., "Enabling Accurate Dynamic Specification Measurement of High Precision Analog and Mixed-Signal Communication Devices on Low Cost ATE," Proceedings, TECHCON, October 2005.

229. Srinivasan, G., Halder, A., Chatterjee, A. and Cherubal, S., "Low Cost Alternate Test approaches for Fast System Level Specification Tests of RF Transceivers," Proceedings, TECHCON, October 2005.

230. Ashouei, M.; Chatterjee, A.; Singh, A.D. and De, V., "A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS," Proceedings, International Conference on Computer Design, Austin, TX, October 2005, pp. 567 - 573.
231. Bhattacharya, S., Senguttuvan, R. and Chatterjee,A., "Production Test Enhancement Techniques for MB-OFDM Ultra-wide Band (UWB) Devices: EVM and CCDF," Proceedings, International Test Conference, Nov 2005, Austin, TX, pp. 236-245.

232. Goyal, S. and Chatterjee A., "Test Time Reduction Of Successive Approximation Register A/D Converter By Selective Code Measurement," Proceedings, International Test Conference, Nov 2005, Austin, TX.

233. Halder, A. and Chatterjee, A., "Low Cost Production Test of BER for Wireless Receivers," Proceedings, 14th Asian Test Symposium, Kolkata, India, December 2005, pp. 64-69.

234. Han, D. H. and Chatterjee, A., "Robust Built-In Test of RF ICs Using Envelope Detectors," Proceedings, 14th Asian Test Symposium, Kolkata, India, December 2005, pp. 2-7.

235. Goyal, S., Chatterjee, A. and Purtell, M., "Alternative Test Methodology for High-Speed A/D Converter Testing on Low Cost Tester," Proceedings, 14th Asian Test Symposium, Kolkata, India, December 2005, pp. 14-17.

236. Bhattacharya, S., Natarajan, V., Nair, S. and Chatterjee, A., "Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms," Proceedings, VLSI Design Conference, Hyderabad, India, January 2006, pp. 729-733.

237. Halder, A. and Chatterjee, A., "Low Cost Production Testing of Wireless Transmitters," Proceedings, VLSI Design Conference, Hyderabad, India, January 2006, pp. 437-442.

238. Ashouei, M.; Chatterjee, A.; Singh, A.D.; De, V. and Mak, T.M.; "Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design, " Proceedings, VLSI Design Conference, Hyderabad, India, January 2006, pp. 606-612.

239. Srinivasan, G., Taenzler, F. and Chatterjee, A., "Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms," Proceedings, Design Automation and Test in Europe , Munich, Germany, March 2006, pp. 1-6.

240. Srinivasan, G., Chatterjee, A. and Taenzler, F., "Alternate Loop-Back Diagnostic Tests for Wafer Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures," Proceedings of the VLSI Test Symposium, May 2006, pp. 222-227.

241. Natarajan, V., Bhattacharya, S. and Chatterjee, A., "Alternate Electrical Tests for Extracting Parameters of MEMs Accelerometer Sensors, " Proceedings, VLSI Test Symposium, May 2006, pp 192-198.

242. Ashouei, M.; Bhattacharya, S.; and Chatterjee, A;, "Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction," Proceedings, VLSI Test Symposium, May 2006, pp. 208-213, Berkeley, CA.

243. Han, D. H., Bhattacharya, S., Goyal, S. and Chatterjee, A., "Low Cost Parametric Failure Diagnosis of RF Transceivers," Proceedings, European Test Symposium, May 2006, pp.205 212.

244. Ashouei, M., Bhattacharya, S., and Chatterjee, A., "Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study," Proceedings, European Test Symposium, May 2006, pp. 35 - 42, Southampton, UK.

245. Goyal, S., Chatteree, A. and Atia, M., "Reducing Sampling Clock Jitter to Improve SNR Performance of A/D Converters in Production Test," Proceedings, European Test Symposium, May 2006, pp. 165-172.

246. Natarajan, V., Srinivasan, G., and Chatterjee, A., "On-line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data", Proceedings 12th International IEEE On-line Testing Symposium, pp 159-165, July 2006.

247. Senguttuvan, R., Bhattacharya, S., and Chatterjee, A., "A Built-in Test-Based Reconfiguration for Wireless Systems for Increased Quality of Service", Proceedings of 49th IEEE International Midwest Symposium on Circuit and Systems, San Juan, Puerto Rico, Aug 6-9, 2006, pp. 633-637.

248. Datta, R., Abraham, J.A., Diril, A.U., Chatterjee, A., and Nowka, K., "Adaptive Design for Performance-Optimized Robustness," Proceedings of International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2006, pp. 3 - 11, Arlington, VA, pp. 3-11.

249. Akbay, S.S., Torres, J.L., Rumer, J.M., Chatterjee, A. and Amtsfield, J. "Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation," Proc. International Test Conference, Santa Clara, CA, November 2006. pp. 1-10.

250. Goyal, S., Chatterjee, A. and Shieh, Y., "Enhanced A/D Converter Signal-to-Noise Ratio Testing in the Presence of Sampling Clock Jitter," Proceedings, 15th Asian Test Symposium, Fukuoka, Japan, Nov. 2006, pp. 307-312.

251. Ashouei, M., Nisar, M., Chatterjee, A., Singh, A.D., and Diril, A., "Probabilistic Self Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations," International Conference on VLSI Design, Jan. 2007, Bangalore, India, pp. 711-716.

252. Ashouei, M., Singh, A.D., and Chatterjee, A., "A Defect-Tolerant Architecture for End of Roadmap CMOS," European Test Symposium, May 2007, Freiburg, Germany.).

253. Ashouei, M., Bhattacharya, S., and Chatterjee, A., "Probabilistic Compensation for Digital Filters under Pervasive Noise-Induced Operator Errors," VLSI Test Symposium, May 2007, Berkeley, CA, pp. 125-130.

254. Natarajan, V., Srinivasan, G., Chatterjee, A., and Force, C. "Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios", Proceedings of 25th International IEEE VLSI Test Symposium, May 2007, pp. 297-302.

255. Choi, H., Han, D., and Chatterjee, A., "Enhanced Resolution Jitter Testing Using Jitter Expansion," Proc. IEEE VLSI Test Symposium, May 2007, Berkeley, CA, pp. 104-109.

256. Senguttuvan, R., and Chatterjee, A., "Alternate Diagnostic Testing and Compensation of Transmitter Performance using Response Detection", Proceedings of 25th IEEE VLSI Test Symposium, Berkeley, California, May 2007, pp.395-400.

257. Ashouei, M., Singh, A. D, Chatterjee, A., "Post-Fabrication Adaptation to Manufacturing Defects and Process Variations", TECHCON 2007 Proceedings, September 10 - 12, 2007, Austin, TX.

258. Nisar M., Ashouei M., Chatterjee A., "Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums", IOLTS, July 2007, Crete, Greece, pp 173-182.

259. Senguttuvan, R., Chatterjee, A., "Low Cost Test, Diagnosis and Tuning for RF Systems", Proceedings of Techcon, Austin, TX, Sep 2007.

260. Senguttuvan, R., Sen. S., Chatterjee, A., "VIZOR: Virtually Zero Margin Adaptive RF for Ultra Low Power Wireless Communication," IEEE International Conference on Computer Design, Lake Tahoe, CA, Oct 2007.

261. Akbay, S. S. and Chatterjee, A., "Fault-Based Alternate Test of RF Components", ICCD'07, Lake Tahoe, CA, Oct 2007.

262. Srinivasan, G. and Chatter5jee, A., "Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources, "IEEE Asian Test Symposium, Beijing, China, October 2007, pp. 139-142.

263. Akbay, S. S., Sen, S. and Chatterjee, A., "Testing RF Components with Current Signatures," IEEE Asian Test Symposium, Beijing, China, October 2007, pp. 393-398.

264. Sen, S., Senguttuvan, R. and Chatterjee, A.," Feedback Driven Adaptive Power Management for Minimum Power Operation of Wireless Receivers" IEEE International Conference on Electronics, Circuits and Systems, December 2007.

265. Goyal, A., Swaminathan, M., Ward, C., White, G., Chatterjee, A.,"A Novel Method for Testing Integrated RF Substrates", IEEE Asia-Pacific Microwave Conference (APMC), December 2007, pp. 277-280.

266. Nisar M., Senguttuvan, R., Chatterjee A., "Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors", International Conference on VLSI Design, January 2008, Hyderabad, India.

267. Senguttuvan, R., Sen, S. and Chatterjee, A.,"Concurrent Multi-Dimensional Adaptation for Low-Power RF in Wireless Devices," VLSI Design Conference, Hyderabad, India, January 2008.

268. Ashouei M., Singh, A.D. and Chatterjee, A., "Reconfiguring CMOS as Pseudo
n/p-MOS for Defect Tolerance in Nano-Scale CMOS", VLSI Design Conference, Hyderabad, India, January 2008.

269. Shreyas Sen, Rajarajan Senguttuvan, Abhijit Chatterjee," Concurrent PAR and Power Amplifier Adaptation for Power Efficient Operation of WiMAX OFDM Transmitters," IEEE Radiowireless 08, January 2008.

270. Natarajan, V., Senguttuvan, R., Sen, S. and Chatterjee, A., "ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-ends", IEEE VLSI Test Symposium, May 2008 (to appear).

271. Nisar, M. and Chatterjee, A., "Test Enabled Process Tuning for Adaptive Baseband OFDM Processor", IEEE VLSI Test Symposium, May 2008 (to appear)

272. Choi, H. and Chatterjee, A., "Digital Bit Stream Jitter Testing Using Jitter Expansion," Proceediongs, Design Automation and Test in Europe, May 2008, (to appear).

273. Sen, S and Chatterjee, A., "Design of Process Variation Tolerant Radio Frequency Low Noise Amplifier, " International Symposium on Circuits and Systems, June 2008 (to appear).

274. Nisar, M., and Chatterjee, A., "Process Tolerant Adaptive Wordlength Architecture and Control Algorithms for Low Power Operation of Baseband OFDM Processor", DAC 2008 (Submitted ).

275. Lee, D., Senguttuvan, R., and Chatterjee, A., "Efficient Method for Predicting Gain, IIP3, Phase Noise, and EVM of Wireless OFDM Polar Transceivers", IEEE European Test Symposium 2008 (submitted).

276. Senguttuvan, R., Choi, H., Han, D.H. and Chatterjee, A., "Efficient Built-in Test of Phase/Frequency Modulated RF Transmitters Using Embedded Rectifier-Integrator Sensors", IEEE European Test Symposium 2008 (submitted).

277. Sen,S., Natarajan,V.,Senguttuvan,R.,Chatterjee,A., "Pro-VIZOR: Process Tunable Virtually Zero Margin Low Power Adaptive RF for Wireless Systems", DAC 2008 (Submitted ).

278. Goyal, A., Swaminathan, M., Chatterjee, A.,"A Novel Low Frequency Low Cost Testing Methodology for High Frequency Passive Circuits", DAC 2008 (Submitted ).

Other Publications:
279. Roy, K. and Chatterjee, A., "Guest Editors' Introduction: Low-Power VLSI Design," IEEE Design and Test of Computers, Winter 1994, pp. 6-7.

Workshop Papers and Presentations:

280. Chatterjee, A., Kim, B., and Nagi, N., "Towards Design of Repairable Linear Analog Circuits," International Mixed-Signal Testing Workshop, Paris, France, June 1995, pp. 40-43.

281. Kim, B., Chatterjee, A., and Swaminathan, M., "A New Technique for Testing MCM Substrates," IEEE and ISHM MCM Advanced Technology Workshop, September 1995.

282. Kao, W., Voorakaranam, R., and Chatterjee, A., "AHDL-Based Analog Behavioral Fault Modeling and Simulation," IEEE High-Level Design Validation and Test Workshop, 1996.

283. Variyam, P. and Chatterjee, A., "Fast Fault Simulation of Linear Analog Systems Using Polynomial Waveform Representations," IEEE International Mixed-Signal Testing Workshop, May 1996, pp. 11-16.

284. Pendurkar, R., Chatterjee, A., and Tovey, C., "New Heuristic Approach for Efficient Single Probe Routing for MCM Substrate Test," MCM Test III Advanced Technology Workshop, September 1996.

285. Voorakaranam, R., Gomes, V., and Cherubal, S., "Hierarchical Fault Simulation of Feedback Embedded Analog Circuits with Approximately Linear to Quadratic Speedup," International Mixed-Signal Testing Workshop, July 1997, pp. 48-59.

286. Yoon, H., Chatterjee, A., Swaminathan, M., and Hughes, J. L. A., "Catastrophic Fault Diagnosis for Embedded RF-Passives Using Single Point Probing," IMAPS Advanced Technology Workshop on MCM Test IV, September 1997.

287. Pendurkar, R. and Chatterjee, A., "A Reconfiguration Technique for BIST of MCM Interconnects," IMAPS Advanced Technology Workshop on MCM Test V, September 1997.

288. Variyam, P. and Chatterjee, A., "Generalized Approach for Test Point Selection in Analog and Mixed-Signal Circuits Using Measurement Synthesis," International Test Synthesis Workshop, March 1998.

289. Pendurkar, R., Chatterjee, A., and Zorian, Y., "A Novel DFT Scheme for Performance Testing of MCMs," International Test Synthesis Workshop, March 1998 .

290. Hou, J. and Chatterjee, A., "CONCERT: A Concurrent Fault Simulator for Analog Circuits," IEEE International Mixed-Signal Testing Workshop, pp. 134-141, June 1998.

291. Variyam, P. and Chatterjee, A., "Test Stimulus Generation for Analog Circuits Using Genetic Optimization," IEEE International Mixed-Signal Testing Workshop, June 1998.

292. Xuan, X., Singh, Chatterjee, A. and Singh, A. D., "Reliability and Hit-Spot Analysis for Analog ICs Under Electromigration and Hot-Carrier Degradation," IEEE International Mixed-Signal Testing Workshop, pp. 192-196, June 2001.

293. Voorakaranam, R. and Chatterjee, A., "A Signature Test Framework for Rapid Production Testing of RF Circuits," Wireless Test Workshop, November 2001.

294. Bhattacharya, S. and Chatterjee, A., "Constrained Specification-based Test Stimulus Generation for Analog Circuits using Nonlinear Performance Prediction Models," Proceedings, DELTA 2002, Christchurch, New Zealand, March 2002, pp. 10-15.

295. Bhattacharya, S. and Chatterjee, A., "Wafer-Probe and Assembled Package Test Co-Optimization for Minimal Test Cost," IEEE International Mixed-Signal Testing Workshop, Montreaux, Switzerland,June 2002.

296. Akbay, S. and Chatterjee, A, "Optimal Multisine Tests for RF Amplifiers," IEEE International Workshop on Test of Wireless Circuits and Systems, October 2002.

297. Halder, A. and Chatterjee, A., "Automated Test Generation and Concurrent Test Point Selection for Specification Based Test of Analog Circuits", Proc. Latin American Test Workshop, Natal, Brazil, Feb 2003.

298. Seo, C. S. and Chatterjee, A., "Free-Space Optical Interconnect for High Performance MCM Systems," IWSOC, 2003.

299. Halder, A., Bhattacharya, S. and Chatterjee, A., "Alternate Test Generation for Specification Test of RF Circuits," IEEE International Mixed-Signal Testing Workshop, Seville, Spain, June 2003.

300. Xuan, X., Chatterjee, A. and Singh, A. D., "Calibration of Mixed-Signal Reliability Simulator Using Burn-In Experiments," IEEE International Mixed-Signal Testing Workshop, Seville, Spain, June 2003.

301. Bhattacharya, S. and Chatterjee, A., "A Fast Process Diagnosis Method Using a Diagnosis Core," IEEE International Mixed-Signal Testing Workshop, Seville, Spain, June 2003.

302. Bhattacharya, S., Srinivasan, G., Cherubal. S. and Chatterjee, A., "Test Time Reduction for ACPR Measurement of Wireless Transceivers Using Periodic Bit Stream Sequences," Proceedings, 2nd International Workshop on Electronic Design, Test and Applications (DELTA), Perth, Australia, January 2004, pp. 372-377.

303. Srinivasan, G., Goyal, S. and Chatterjee, A., "Enhancing Alternate Test Performance for Analog Circuits Using Reconfiguration for Testability," Proceedings, 5th Latin American Test Workshop, Cartagena, Colombia, March 2004, pp. 134-139 (Received Best Paper Award).

304. Ashouei, M., Chatterjee, A. and Singh, A. D., " A Test Data Compression Technique and Its Application to Scan," Proceedings, Defect Based Testing Workshop, April 2004.

305. Bhattacharya, S. and Chatterjee, A., "Built-In Test of Analog and RF Circuits Using Embedded Sensors," Proceedings, 5th IEEE International Workshop on Test Resource Partitioning, Napa Valley, CA, April 2004.

306. Han. D. H., Halder, A. and Chatterjee, A., "Test Elimination Using Redundancy Análysis for Specification Test of Analog Circuits," Proceedings, 10th International Mixed-Signal Testing Workshop, Pórtland, Oregon, June 2004, pp. 69-75.

307. Srinivasan, G. Halder, A., Bhattacharya, S. Goyal, S. and Chatterjee, A., "Loopback Test of RF Transceivers Using Periodic Bit Sequences: An Alternate Test Approach," Proceedings, 10th International Mixed-Signal Testing Workshop, Pórtland, Oregon, June 2004, pp. 69-75.

308. Akbay, S. and Chatterjee, A., "Alternate Test of RF Mixers by Current Signatures," Digest of 3rd Workshop on Test of Wireless Circuits and Systems, Fort Worth, TX, June 2004.

309. Han, D. H. and Chatterjee, A., "Simulation-in-the-loop Analog Circuit Sizing Method Using Adaptive Model-Based Simulated Annealing," Proceedings, 4th IEEE International Workshop on Systems-on-Chip, Banff, Alberta, Canada, July 2004, pp. 127-130.

310. Akbay, S. and Chatterjee, A., " Temperature Compensated Built-In Alternate Test of RF Modules," Digest of 1st IEEE International GHz/Gbps Test Workshop, Charlotte, NC, October 2004.

311. Senguttuvan, R., Bhattacharya, S., and Chatterjee, A., "Effect of Manufacturing Process Variations on UWB Transceiver Specifications" Proceedings, Wireless Test Workshop, June 25-27, 2005, Cannes "Cote d'Azur", France.

312. Han, D. H., Chatterjee, A., Akbay, S. and Bhattacharya, S, "Robust Built-In Alternate Test of RF ICs using Envelope Detectors," Proceedings, International Mixed Signals Testing Workshop, June 25-27, 2005, Cannes "Cote d' Azur", France, pp. 123-128.

313. Bhattacharya, S., Senguttuvan, R., Chatterjee, A., "Production Test Enhancement Techniques for MB-OFDM Ultra-wide band Devices: EVM and CCDF", Proceedings, International Mixed Signals Testing Workshop, June 25-27, 2005, Cannes "Cote d' Azur", France, pp. 199-205.

314. Goyal, S. and A. Chatterjee, "Alternate Testing of High Speed A/D Converters Dynamic Specifications Using Low Cost Testers," Proceedings, International Mixed Signals Testing Workshop, June 25-27, 2005, Cannes "Cote d' Azur", France, pp. 106-112.

315. Han, D. H., Bhattacharya, S., Halder, A. and Chatterjee, A., "Built-in at-speed test and diagnosis of wireless transceiver systems," Proceedings, Gigahertz Test Workshop, Austin, TX (with ITC), Nov. 2005, pp.45-50.

316. Ashouei, M.; Bhattacharya, S. and Chatterjee, A;, "Low Cost Probabilistic Error Correction in Linear Digital Filters Using Checksum Codes," Proceedings, Latin American Test Workshop, Buenos Aires, Argentina, March 2006.

317. Akbay, S.S., and Chatterjee, A. "Comprehensive Catastrophic and Parametric Fault Testing Using the Alternate Test Approach," Proc. IEEE International Workshop on Current & Defect Based Testing, Santa Clara, CA, USA, Nov. 2006, pp. 45-50.

318. Senguttuvan, R., Bhattacharya, S., Choi, H., Han, D.H., Chatterjee, A., "Adaptive OFDM Wireless Receiver Front-end: Self Correction and self Tuning", Proceedings of International Mixed-Signal Testing Workshop, Edinburgh, United Kingdom, Jun 2006, pp167-173.

319. Bhattcharya, S., Senguttuvan, R., Chatterjee, A.,Singh, A., "Efficient Comparison-Based Wafer Probe Test of Analog/Rf Circuits using Response Features", Proceedings of International Mixed-Signal Testing Workshop, Edinburgh, United Kingdom, Jun 2006, pp236-237.

320. Han, D.H., Bhattacharya, S., Chatterjee, A., "Built-in RF Transceiver Test and Diganosis using Transient Envelope Detection and Sampling, Proceedings of International Mixed-Signal Testing Workshop, Edinburgh, United Kingdom, Jun 2006, pp167-173.pp. 250-257. Senguttuvan, R., Bhattacharya, S., Chatterjee, A., "A Built-in Test-based Reconfiguration Scheme for UWB receivers for Increased Quality of Service (QoS)", Wireless Test Workshop 2007, Berkeley, CA.

321. Chatterjee, A. Bhattacharya, S., Han, D., Halder, A., Akbay, S., Goyal, S., Senguttuvan, R., Srinivasan, G., Natarajan, V., Choi, H., "Low-Cost Built-in Test of Wireless Transceivers", IEEE MTT Workshop on On-chip/Off-Chip DC, RF and Microwave Measurement Modules for RFIC, SoC and SiP Self-Characterization, Self-Test, Debug and Diagnosis , June 2007.

322. Senguttuvan, R., Natarajan, V., Chatterjee, A., " Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems", Proceedings of International Mixed Signals Testing Workshop, 2007, Povoa de Varzim, Portugal, Jun 2007, pp. 80-85.

323. Senguttuvan, R., Choi, H., Han, D., Chatterjee, A., "A Novel Built-in Test Technique for Phase/Frequency Modulated RF Transmitters", Proceeding of 3rd International GHz/Gbps Test Workshop, Povoa de Varzim, Portugal, Jun 2007.

324. Senguttuvan, S. Nisar, M, Sen, S., Natarajan, . and Chatterjee, A., "End-to-End Test-Enabled Low-Power Adaptation for Wireless OFDM Systems, " IEEE Workshop on Silicon Errors in Logic-System Effects, June 2008 (submitted).