GIGASCALE INTEGRATION GROUP

A prospectus for Gigahertz Gigascale Integration

by

James D. Meindl

Throughout the past 36 years, silicon microelectronics has advanced at an utterly unprecedented exponential rate in both productivity and performance. The number of transistors per chip has increased by about seven orders of magnitude while the price range of a chip has remained virtually constant and the switching energy per binary transition has decreased by about five decades. A compelling question facing the rapidly growing 100 billion dollar world-wide semiconductor industry is: "How much longer will the laws of physics permit this advance to continue?"

My response is that opportunities for multi-billion transistor chips in the early 21st century will be governed by a hierarchy of physical limits. The five levels of this hierarchy can be codified, from bottom-up, as fundamental, material, device, circuit and system.

At the first level of the hierarchy there are three critical fundamental limits derived from thermodynamics, from the uncertainty principle of quantum mechanics and from electromagnetics. The limit from electromagnetics is defined by the propagation velocity of an electromagnetic wave and currently is the most binding of the three fundamental limits. It will become even more so in the future due to its unyielding constraint on interconnect delay.

At the second level, there are three key material limits imposed by semiconductors. The first of these is a switching energy limit which is defined as the minimum amount of energy that must be stored in a cubic volume of material in order to support a binary transition of one volt. This energy is about 10 electron-volts and is 20% larger for Si than for GaAs. The second key material limit is a transit time defined as the interval required for an electron to transport through the cubic volume in question. This time is about 1/3 picosecond and is 33% larger for Si than for GaAs. The third key material limit is a thermal conduction limit defined as the intrinsic switching delay per unit of heat removal of a generic device. This heat- conduction-limited delay is about 3 times larger for GaAs than for Si. This disadvantage of GaAs is a result of its three times larger thermal resistivity compared with Si. The message conveyed by these numbers is that Si is the semiconductor material of the future.

At the third level of the hierarchy, the most critical device limits are those imposed by the Mosfet and are defined largely by its minimum allowable channel length L. Calculations and some recent experimental data show that L for a bulk Mosfet with a simple uniform channel doping profile is about 100nm. For a retrograde channel Mosfet, this value drops to about 50nm. For a double gate SOI Mosfet, a device that we do not yet know how to manufacture, the projected L is about 25nm. Finally, for a bulk Mosfet with a high permittivity gate dielectric stack, L is about 25nm. The strong message conveyed by these projections is that we have many, many years ahead until physical limits forbid further Mosfet scaling, perhaps more than another two decades until about 2020.

Another critical limit at the device level is defined by the response time of an interconnect that must be modeled as a canonical distributed resistance-capacitance network. For example, for 1.0 micron technology, the 10 picosecond response time of a Mosfet is ten times larger than the response time of a 1.0 mm long interconnect. But, for 0.1 micron technology, the 100 picosecond response time of a 1.0 mm interconnect is 100 times larger than that of a Mosfet. The message that these numbers convey is that from now on interconnections are more important than transistors!!!

At the fourth level of the hierarchy, there are four key generic circuit limits including logic gate static transfer characteristics, switching energy and propagation delay as well as global interconnect response time. In concert, these limits dictate the smallest allowable supply voltage for a CMOS logic gate that is rigorously designed for minimum total energy consumption subject to a required level of performance and operating temperature range. For bulk silicon technology, this supply voltage range is 0.5-1.0volts for a wide variety of systems.

The fifth level of the hierarchy encompasses its most restrictive constraints including five key generic system limits involving architecture, critical path switching energy, package cooling capacity, clock frequency and chip size. The paramount message conveyed by these limits is the urgent necessity to invent new circuit configurations and new system architectures that minimize the use of semi-global and global interconnections in order to enable Gigascale Integration at Gigahertz clock frequencies or GGSI.

In conclusion, opportunities for GGSI in the early 21st century will be governed by a five-level hierarchy of physical limits which clearly indicate technical feasibility. The decisive issue then becomes whether or not the multi-billion dollar investments needed to bring GGSI to fruition will be deemed acceptable business risks by corporations and nations.