1. J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, and P. A. Kohl, "Interconnect Opportunities for Gigascale Integration," IBM J. Res. & Dev., vol. 46, pp. 245-263, Mar/May 2002.

2. J. D. Meindl et al., “Interconnecting device opportunities for gigascale integration (GSI),” Proc. IEDM, pg. 23.1.1, Dec. 2001.

3. J. D. Meindl, Special Issue on the Limits of Semiconductor Technology," Proc. IEEE, vol. 89, pp. 223-226, Mar. 2001.

4. J. Davis et al., "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,"Proc. IEEE, vol. 89, pp. 305-324, Mar. 2001.

5. J. D. Meindl and J. A. Davis, "The Fundamental Limit on Binary Switching Energy for Terescale Integration (TSI)," IEEE. J. Solid-State Circuits, pp. 1515-1516, Oct. 2000.

6. J. D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proc. IEEE, vol. 83, pp. 619-635, Apr. 1995.

7. Retrospect Figures (Enlarged)

Best Paper Awards

Recent Ph.D. Theses

1. A.V. Mule, "Volume Grating Coupler-Based Optical Interconnect Technologies for Polylithic Gigascale Integration," Ph.D. Dissertation, 2004, Georgia Institute of Technology. TOC

2. J. Joyner, "Opportunities and Limitations of Three-dimensional Integration for Interconnect Design," Ph.D Dissertation, 2003, Georgia Institute of Technology.

3. Q. Chen, "Scaling Limits and Opportunities for Double-Gate MOSFETs," Ph.D. Dissertation, 2003, Georgia Institute of Technology.

4. R. Venkatesan, “Multilevel Interconnect Architectures for Gigascale Integration (GSI),” Ph.D. Dissertation, 2003, Georgia Institute of Technology.

5. B. Austin, "Performance Analysis and Scaling Opportunities of Bulk CMOS Inversion and Accumulation Devices," Ph.D. Dissertation, 2001, Georgia Institute of Technology.

6. K. Bowman, "A Circuit Level Perspective of Opportunities and Limitations for Gigascale Integration," Ph. D. Dissertation, 2001, Georgia Institute of Technology.

7. A. Bhavnagarwala, "Voltage Scaling Constraints for Static CMOS Logic and Memory Circuits," Ph. D. Dissertation, 2001, Georgia Institute of Technology.

8. P. Zarkesh-Ha, "Global Interconnect Modeling for a Gigascale System-on-a-Chip (GSoC), " Ph. D. Dissertation, 2001, Georgia Institute of Technology.

9. C. S. Patel, " Compliant Wafer-Level Package (CWLP)," Ph.D. Dissertation, 2001, Georgia Institute of Technology.

10. L. Codrescu, "ATLAS: A Dynamically Parallelizing Chip-Multiprocessor for Gigascale Integration," Ph. D. Dissertaion, 2000, Georgia Institute of Technology.

11. S. M. Chai, " Real Time Image Processing on Parallel Arrays for Gigascale Integration," Ph. D. Dissertation, 1999, Georgia Institute of Technology.

12. J. Davis, "A Hierarchy of Interconnect Limits and Opportunities for Gigascale Integration (GSI)," Ph. D. Dissertation, 1999, Georgia Institute of Technology.

13. X. Tang, "Intrinsic and Extrinsic Parameter Fluctuation Limits on Gigascale Integration (GSI), " Ph. D. Dissertation,1999, Georgia Institute of Technology.

14. J.C.Eble III., "A Generic System Simulator with Novel On-Chip Cache and Throughput Models for Gigascale Integration," Ph. D. Dissertation, 1998, Georgia Institute of Technology.

High Frequency and Size Effects in Electrical Interconnects

1. R. Sarvari, A. Naeemi, J.D. Meindl, "General Compact Model for Bit-Rate Limit of Electrical Interconnects Considering DC Resistance, Skin Effect and Surface Scattering"; Proceedings of the IEEE International Interconnect Technology Conference, June, 2004.

2. R. Sarvari, J.D. Meindl, "On the study of anomalous skin effect for GSI interconnections"; Proceedings of the IEEE International Interconnect Technology Conference, June 2-4, 2003, pp 42 - 44.

Testing Chips with Electrical and Optical I/O Interconnects

1. H. Thacker, O. Ogunsola, M. Bakir, J. Meindl, "Probe Module for Wafer-level Testing of Gigascale Chips with Polymer Pillar-based Electrical and Optical I/O Interconnects," to be published, in Proc. SRC TECHCON, Portland, OR, October, 2005.

2. H. Thacker, O. Ogunsola, M. Bakir, J. Meindl, "Probe Module for Wafer-level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects," to be published, in Proc. ASME InterPACK, San Francisco, CA, July 2005.

3. H. Thacker, O. Ogunsola, M. Bakir, J. Meindl, "High-Density Probe Substrate for Testing Optical Interconnects," to be published, in Proc. IEEE IITC, San Francisco, CA, June 2005.

4. H. Thacker, A. Mule', R. Villalaz, T. Gaylord, J. Meindl, "Compliant Probe Substrates with Two-Material, Air-Clad, Grating-in-Waveguide Optical I/O Interconnects," in Proc. 17th Annual Meeting IEEE LEOS, Puerto Rico, November 2004.

5. Hiren D. Thacker, Muhannad S. Bakir, David Keezer, Kevin P. Martin, James D. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in Proc. Electronic Components and Technol. Conf., 2002, pp. 1188-1193.

Power Distribution for Gigascale Integration

1. K. Shakeri and J. D. Meindl, "Relative inductance extraction method," presented at Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 3-6 Oct. 2004, Orlando, FL, USA, 2004.

2. K. Shakeri, M. Bakir, and J. D. Meindl, "Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution," presented at Proceedings. IEEE International SOC Conference, 12-15 Sept. 2004, Santa Clara, CA, USA, 2004.

3. K. Shakeri, Reza Sarvari, J.D. Meindl, “A Compact Substrate Spreading Resistance Model for SoC,” IEEE International SOC Conference, Sep 2003.

4. K. Shakeri, J.D. Meindl, “Compact Physical IR-Drop Models for GSI Power Distribution Networks,” IEEE Intl. Interconnect Technology Conf., June 2003.

5. K. Shakeri, J.D. Meindl, “Three Phase Domino Logic Circuit,” ASIC/SOC Conference, Sep. 2002.

6. K. Shakeri, J.D. Meindl, “Temperature Variable Supply Voltage for Power Reduction,” IEEE Computer Society Symposium on VLSI, April 2002.

7. K. Shakeri, J.D. Meindl, “A Compact Delay Model for Series-Connected MOSFETs,” Great Lakes Symposium on VLSI,  April 2002.

Sea of Polymer Pillar Input/Output Interconnects

1. M. S. Bakir and J. D. Meindl, "Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections," presented at 2004 IEEE LEOS Annual Meeting Conference Proceedings, 7-11 Nov. 2004, Rio Grande, Puerto Rico, 2004.

2. M. S. Bakir and J. D. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Transactions on Electron Devices, vol. 51, pp. 1069-77, 2004.

3. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors," IEEE Transactions on Electron Devices, vol. 51, pp. 1084-90, 2004.

4. M. S. Bakir and J. D. Meindl, "Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration," presented at 2004 Proceedings. 54th Electronic Components and Technology Conference, 1-4 June 2004, Las Vegas, NV, USA, 2004.

5. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, K. P. Martin, P. A. Kohl, and J. D. Meindl, "Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics," presented at 2004 Proceedings. 54th Electronic Components and Technology Conference, 1-4 June 2004, Las Vegas, NV, USA, 2004.

6. Muhannad S. Bakir, Thomas K. Gaylord, Oluwafemi O. Ogunsola, E. G. Glytsis, and James D. Meindl, "Optical transmission of polymer pillars for chip I/O optical interconnections," IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.

7. M. S. Bakir, A. V. Mule', T. K. Gaylord, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," presented at Proceedings of IEEE International Solid-State Circuits Conference, 9-13 Feb. 2003, San Francisco, CA, USA, 2003.

8. Muhannad S. Bakir, Thomas K. Gaylord, Kevin P. Martin, James D. Meindl, "Sea of Polymer Pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp.1567-1569, Nov. 2003

Genesys

1. S. Nugent, "An Ultra-Compact Empirical Model for Throughput Projection for Gigascale Integration," TECHCON 2000, Sept. 2000.

2. J.C.Eble III., Ph.D. Dissertation, "A Generic System Simulator with Novel On-Chip Cache and Throughput Models for Gigascale Integration". 1998, Georgia Institute of Technology

3. Genesys Users Manual

Sea of Leads (SoL) Ultra-High Density I/O Wafer-Level Packaging

1. B. Dang, C. Patel, H. Thacker, M.Bakir, K. Martin, J. Meindl, "Optimal Implementation of Sea of Leads (SoL) Compliant Interconect Technology," Proceedings of IEEE International Interconnect Technology Conference, June 2004.

2. Muhannad S. Bakir, Hollie A. Reed, Hiren D. Thacker, Paul A. Kohl, Kevin P. Martin, and James D. Meindl, "Sea of Leads (SoL) ultrahigh density wafer level chip input/output interconnections," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.

3. David C. Keezer, Chirag S. Patel, Muhannad S. Bakir, Qing Zhou, James D. Meindl, "Electrical test strategies for a wafer-level packaging technology," IEEE Trans. Electronics Packaging Manufacturing, vol. 26, no. 4, pp. 267-272, Oct. 2003.

4. Muhannad S. Bakir, Hollie Reed, Anthony Mule’, Joseph Jayachandran, Paul Kohl, Thomas Gaylord, Kevin Martin, and James Meindl, “Chip-to-module interconnections using 'Sea of Leads' technology,” MRS Bulletin, vol. 28, pp. 61-67, Jan. 2003. [invited]

5. M. S. Bakir, A. V. Mule', H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "SoL Compliant Wafer-level Package Technologies," Semiconductor International Magazine, pp. 61-64, Apr. 2002.

6. M. S. Bakir, H. A. Reed, A. V. Mule', P. A.  Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads characterization and design for
   compatibility for board level optical waveguide interconnection" IEEE Custom Integrated Circuits Conference. Orlando, FL: pp. 491-495, May 2002.

7. M. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads ultra-high density compliant wafer level
   packaging technology," IEEE Electronic Components and Technology Conference. San Diego, Ca: pp. 1087-1094, May 2002.

8. M. S. Bakir, H. D. Thacker, Z. Zhou, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of lead microwave characterization
   and process integration with FEOL & BEOL," IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 116-118, June 2002.

9. H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, "Compliant wafer-level package (CWLP) with embedded air-gaps for Sea-of-Leads (SoL) interconnections," Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 151-153, June 2001.

10. M. S. Bakir, C. S. Patel, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Ultra High I/O Density Package: Sea of Leads (SoL)," International Conference on High Density Interconnects (HDI), Apr. 2001.

11. A. Naeemi, C. S. Patel, M. S. Bakir, P. Zarkesh-Ha, K. P. Martin, and J. D. Meindl, "Sea of Leads: A disruptive paradigm for a system on a chip (SoC)," IEEE International Solid State Circuits Conference (ISSCC). San Francisco, CA.: pp.280-281, Feb. 2001.

12. M. Bakir, H. Reed, A. V. Mule', P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads (SoL) Ultra High Density compliant wafer level packaging technology", HDI Expo, Sept. 2001.

Compliant Wafer-Level Packaging

1. C. S. Patel, " Compliant Wafer-Level Package (CWLP)," Ph.D. Dissertation, 2001, Georgia Institute of Technology.

2. C. S. Patel, K. P. Martin, and J. D. Meindl, "Electrical performance of compliant wafer-level package," Proc. 51st Annual Electronic Components and Technology Conference. Orlando, FL: pp. 1380-1383, June 2001.

3. C. S. Patel, K. P. Martin and J. D. Meindl, Optimal Printed Wiring Board Design for High I/O Density Chip Size Packages, 1999 International Printed Circuit Expo (IPC’99), Long Beach Island, California, March, 1999.

4. C.S. Patel, K. P. Martin and J. D. Meindl," Performance issues in high-density printed wiring board design for High I/O Compliant Wafer Level Packages", 2nd Annual Semiconductor Packaging Technologies Symposium, July 1999.

5. C.S. Patel, K. P. Martin and J. D. Meindl, "An analysis of the gap between PWB technology and chip I/O interconnect technology, and a new Wafer Level Batch Packaging Concept", 32 International Symposium on Microelectronics (IMAPS), Oct. 1999.

6. Chirag S. Patel, Review and Analysis of Chip Scale Packages, Ph.D. Qualifying Examination Written Report, Georgia Institute of Technology, December 9, 1998.

Analysis and Optimization of Global Interconnects for Gigascale Integration (GSI)

1. A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)," IEEE Electron Device Letters, vol. 26, pp. 84-6, 2005.

2. A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for GSI," presented at 2004 International Electron Devices Meeting, 13-15 Dec. 2004, San Francisco, CA, USA, 2005.

3. A. Naeemi, J. A. Davis, and J. D. Meindl, "Analysis and optimization of coplanar RLC lines for GSI global interconnection," IEEE Transactions on Electron Devices, vol. 51, pp. 985-94, 2004.

4. A. Naeemi, J. A. Davis, and J. D. Meindl, "Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)," IEEE Transactions on Electron Devices, vol. 51, pp. 1902-12, 2004.

5. A. Naeemi and J. D. Meindl, "An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation," presented at Proceedings of the IEEE 2004 International Interconnect Technology Conference, 7-9 June 2004, Burlingame, CA, USA, 2004.

6. A. Naeemi, J. Xu, A. V. Mule', T. K. Gaylord, and J. D. Meindl, "Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization," IEEE Photonics Technology Letters, vol. 16, pp. 1221-3, 2004.

7. A. Naeemi, J. A. Davis, and J. D. Meindl, “Compact physical models for the worst case crosstalk induced by near and far aggressors in a SoC,” IEEE Intl. ASIC/SOC Conf., Sept. 2003, pp. 199-202.

8. A. Naeemi, R. Venkatesan, and J. D. Meindl, “Optimal global interconnecting devices for GSI,” IEEE Trans. Electron. Devices, pp. 980-987, April 2003.

9. A. Naeemi, A. V. Mule, and J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” IEEE Intl. Interconnect Technology Conf., June 2003, pp. 230-232.

10. A. Naeemi, J. A. Davis, and J. D. Meindl, “Optimal global interconnecting devices for GSI , IEEE IEDM Digest, December 2002, pp. 319-322

11. A. Naeemi, R. Venkatesan, and J. D. Meindl, “System-on-a-chip global interconnect optimization,” Proc. ASIC/SoC Conf., September 2002, pp. 399-403.

12. A. Naeemi, J. A. Davis, J. D. Meindl, “Optimal global interconnecting devices for GSI, IEEE IEDM Digest, December 2002, pp. 319-322.

13. A. Naeemi, J. Davis, and J. D. Meindl, "Analytical models for coupled distributed RLC lines with ideal and non-ideal return paths," Proc. IEEE International Electron Device Meeting. Washington, D.C.: Dec. 2001.

14. A. Naeemi and J. D. Meindl, "An optimal partition between on-chip and on-board interconnects," Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 131-133, June 2001.

15. A. Naeemi, Chirag S. Patel, Muhannad S. Bakir, Payman Zarkesh-Ha, Kevin P. Martin and James D. Meindl, “Sea of Leads: A Disruptive Paradigm for a System-on-a-Chip (SoC)”, IEEE International Solid-State Circuits Conference. pp 280-281, Feb. 2001.

16. A. Naeemi, P. Zarkesh-Ha, C. S. Patel, and J. D. Meindl, “Performance Improvement Using On-Board Wires for On-Chip Interconnects”, IEEE 9th Topical meeting on Electrical Performance of Electronic Packaging. pp 325-328, Oct. 2000.
     

Optical Interconnect Technologies for Polylithic Gigascale Integration

1. A. V. Mule', R. Villalaz, T. K. Gaylord, and J. D. Meindl, "Photopolymer-based diffractive and MMI waveguide couplers," IEEE Photonics Technology Letters, vol. 16, pp. 2490-2, 2004.

2. A. V. Mule, R. Villalaz, T. K. Gaylord, and J. D. Meindl, "Quasi-free-space optical coupling between diffraction grating couplers fabricated on independent substrates," Applied Optics, vol. 43, pp. 5468-75, 2004.

3. A. V. Mule, R. Villalaz, J. P. Jayachandran, P. A. Kohl, T. K. Gaylord, and J. D. Meindl, "Polymer optical interconnect technologies for polylithic gigascale integration," presented at Advanced Metallization Conference 2003 (AMC 2003), 21-23 Oct. 2003 & 29 Sept.-1 Oct. 2003, Montreal, Que., Canada & Tokyo, Japan, 2004.

4. A. V. Mule, R. Villalaz, T. K. Gaylord, and J. D. Meindl, "Two-material, air-clad, grating-in-the-waveguide optical interconnects," presented at Proceedings of the IEEE 2004 International Interconnect Technology Conference, 7-9 June 2004, Burlingame, CA, USA, 2004.

5. A. V. Mule, P. J. Joseph, S.-A. B. Allen, P. A. Kohl, T. K. Gaylord, and J. D. Meindl, "Polymer optical interconnect technologies for polylithic gigascale integration," presented at ESSDERC 2003. Proceedings of the 33rd European Solid-State Device Research - ESSDERC '03, 16-18 Sept. 2003, Estoril, Portugal, 2003.

6. Y-M. Wu, T.K. Gaylord, E.N. Glytsis, J.D. Meindl, " Sensitivity Analysis of Grating Couplers for Gigascale Integration," Proc. Optical Society 2003 (abstract).

7. A. V. Mule’, E. N. Glytsis, T. K. Gaylord, and J. D. Meindl, “Electrical and optical clock distribution networks for high performance microprocessors,” IEEE Trans. Very Large Scale Integration Systems, 2002.

8. A. V. Mule’, A. Naeemi, E. Glytsis, T. Gaylord, and J. D. Meindl, “Towards a comparison between chip-level optical interconnection and board-level electrical exterconnection,” Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 92-94, June 2002.

9. A. V. Mule’, M. Bakir, J. Jayachandran, R. Villalaz, H. Reed, K. Martin, P. Kohl, E. Glytsis, T. Gaylord, J. Meindl, N. Agrawal, S. Ponoth, J. Plawsky, and P. Persans, “Optical waveguides embedded within a sea-of-leads (SoL) wafer-level package,” Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 122-124, June 2002.

10. M. S. Bakir, A. V. Mule', H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "SoL Compliant Wafer-level Package Technologies," Semiconductor International Magazine, pp. 61-64, Apr. 2002.

11. M. S. Bakir, H. A. Reed, A. V. Mule', P. A.  Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads characterization and design for
    compatibility for board level optical waveguide interconnection" IEEE Custom Integrated Circuits Conference. Orlando, FL: pp. 491-495, May 2002

12. P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, and A. V. Mule’, "The Clock Distribution of the Power4 Microprocessor," Proc. IEEE International Solid State Circuits Conference. San Francisco, CA: pp. 144-145, Feb. 2002.

13. A. Mule', S. Schultz, E. N. Glytsis, T. K. Gaylord, and J. D. Meindl, "Input Coupling and Guided-wave Distribution Scheme for Board-level Intra-chip Optical Clock Distribution Network Using Volume Grating Coupler Technology," Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 128-130, June 2001.

14. A. Mule', S. Schultz, T. K. Gaylord, and J. D. Meindl, " An Optical Clock Distribution Network for Gigascale Integration". Proc. IEEE International Interconnect Technology Conference 2000, pp. 6-8, June 2000.

15. A. Mule', S. Schultz, T. K. Gaylord, and J. D. Meindl, " A 10GHz Hybrid Optical/Electrical Clock Distribution Network for Gigascale Integration". LEOS 99' Annual Meeting, pp. 627-628, Nov. 1999.

16. P. Zarkesh-Ha, T. Mule', and J.D. Meindl, "Characterization and Modeling of Clock Skew with Process Variations," IEEE Custom Integrated Circuit Conference, pp. 441-444, May 1999.

Three-Dimensional Interconnect Modeling

1. J. W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J. Davis, and J. D. Meindl, "Impact of three-dimensional architectures on interconnects in gigascale integration," IEEE Trans. Very Large Scale Integration Systems, vol. 9, pp. 922-928, Dec. 2001.

2. J. W. Joyner, P. Zarkesh-Ha, and J. D. Meindl, "A stochastic global net-length distribution for a three-dimensional system-on-a-chip [3D-SoC]," Proc. 14th Annual IEEE ASIC/SOC Conference, pp. 147-151, Sept. 2001.

3. J. W. Joyner, P. Zarkesh-Ha, and J. D. Meindl, "A global interconnect design window for a three-dimensional system-on-a-chip," Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 154-156, June 2001.

4. J. Joyner, P. Zarkesh- Ha, J. A. Davis, and J. D. Meindl, " Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures," Proc., SLIP 2000 Workshop. San Diego, CA: 2001.

5. J. Joyner, P. Z. Ha, J. A. Davis, and J. D. Meindl, " A Three-Dimensional Stochastic Wire Length Distribution for Variable Separation of Strata," Proc., IEEE International Interconnect Technology Conference 2000.

6. J. W. Joyner and J. D. Meindl, "A compact model for projections of future power supply distribution network requirements," presented at Proceedings 15th Annual IEEE International ASIC/SOC Conference, 25-28 Sept. 2002, Rochester, NY, USA, 2002.

7. J. W. Joyner and J. D. Meindl, "Opportunities for reduced power dissipation using three-dimensional integration," presented at Proceedings of the IEEE 2002 International Interconnect Technology Conference, 3-5 June 2002, Burlingame, CA, USA, 2002.

8. J. W. Joyner, R. Venkatesan, J. A. Davis, and J. D. Meindl, "The limits of system improvement through liquid diagonal routing of interconnects," presented at IEEE International Interconnect Technology Conference, 2-4 June 2003, Burlingame, CA, USA, 2003.

9. J. W. Joyner, P. Zarkesh-Ha, and J. D. Meindl, "Global interconnect design in a three-dimensional system-on-a-chip," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 367-72, 2004.

Via Blockage

1. Q. Chen, J. Davis, P. Zarkesh-Ha, and J. Meindl, "A Compact Physical Via Blockage Model", IEEE Trans. VLSI Syst., vol. 8, pp. 689-692, Dec. 2000..

2. Q. Chen, P. Zarkesh-Ha, J. Davis, and J. D. Meindl, "A Novel Via Blockage Model and its Implications,", IEEE International Interconnect Technology Conference 2000, pp. 15-17.

Double-Gate MOSFET Modeling

1. Q. Chen, "Scaling Limits and Opportunities of Double-Gate MOSFETs," Ph.D. Dissertation, 2003, Georgia Institute of Technology.

2. Q. Chen, L. Wang, and J. D. Meindl, "Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs," Solid-State Electronics, vol. 49, pp. 271-4, 2005

3. Qiang Chen; Lihui Wang; Meindl, J.D.,"Physics-based device models for nanoscale double-gate MOSFETs",Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on 2004 Page(s):73 - 79

4. Q. Chen, E. M. Harrell, II, and J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, pp. 1631-7, 2003.

5. Q. Chen, L. Wang, and J. D. Meindl, "Quantum mechanical effects on double-gate MOSFET scaling," presented at 2003 IEEE International SOI Conference. Proceedings, 29 Sept.-2 Oct. 2003, Newport Beach, CA, USA, 2003.

6. Q. Chen, K. A. Bowman, E. M. Harrell, and J. D. Meindl, "Double Jeopardy in the Nanoscale Court?", IEEE Circuits & Devices Magazine, January 2003.

7. Q. Chen and J. D. Meindl, “A comparative Studet of Threshold Variations in Symmetric and Asymmetric Undoped Double-Gate MOSFETs,” Proc. IEEE International SOI Conference,pp. 30-31, October 2002.

8. Q. Chen, L. Wang, and J. D. Meindl, “Impact of High-K Dielectrics on Undoped Double-Gate MOSFET Scaling,” Proc. IEEE International SOI Conference, pp. 115-116, October 2002.     

9. Q. Chen, B. Agrawal, and J. D. Meindl, “A Comprehensive Analytical Substhreshold Swing (S) Model for Double-Gate MOSFETs,” IEEE    Transactions on Electron Devices, vol. 49, no. 6, pp. 1086-1090, June 2002.

Optimal N-tier Multi-level Interconnect Architectures

1. R. Venkatesan, “Multilevel Interconnect Architectures for Gigascale Integration (GSI),” Ph.D. Dissertation, 2003, Georgia Institute of Technology.

2. R. Venkatesan, J.A. Davis, and J.D. Meindl, "Compact Distributed RLC Interconnect Models - Part IV: Models for Time Delay, Crosstalk, and Repeater Insertion," IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1094-1102, April 2003.

3. R. Venkatesan, J.A. Davis, and J.D. Meindl, "Compact Distributed RLC Interconnect Models Part III: Transients in Single and Coupled Lines with Capacitive Load Termination," IEEE Transactions on Electron Devices, vol. 50, no.4, pp. 1081-1093, April 2003.

4. R. Venkatesan, J. A. Davis, and J. D. Meindl, “Time Delay, Crosstalk and Repeater Insertion Models for High Performance SoC’s,” Proc. ASIC/SoC 2002, Rochester: pp. 404-408, September 2002.

5. R. Venkatesan, "Multilevel interconnect architectures for gigascale integration," Ph.D. Proposal, Georgia Institute of Technology, Apr. 2002.

6. R. Venkatesan, J. A. Davis, and J. D. Meindl, "A physical model for the transient response of capacitively loaded distributed rlc interconnects," Proc. DAC 2002. New Orleans: pp. 736-766, June 2002.

7. R. Venkatesan, J. A. Davis, K. A. Bowman and J. D. Meindl, "Optimal n-tier Multi-level Interconnect Architectures for Gigascale Integration (GSI)", IEEE Trans. VLSI Syst., vol. 9, pp. 899-912, Dec. 2001.

8. R. Venkatesan, J. A. Davis, K. A. Bowman and J. D. Meindl, "Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion," Proc. Intern. Symp. Low Power Electr. Design, pp. 167-172, July 2000.

9. R. Venkatesan, J. Davis and J.D. Meindl, "Optimal Repeater Insertion for N-tier Multi-level Interconnect Architectures," Proc., IEEE International Interconnect Technology Conference 2000, pp. 132-134, June 2000.

10. J. Davis, R. Venkatesan, K. A. Bowman, and J.D. Meindl," Gigascale Integration (GS) Limits and N-tier Multi-level Interconnect Architectural Solutions," International Workshop on the System-Level Interconnect Prediction, pp. 107-112, April 2000 .

11. R. Venkatesan, J. Davis and J.D. Meindl, "Performance Enhancement Through Optimal N-Tier Multilevel Interconnect Architectures", Proceedings of the Twelfth International IEEE ASIC/SOC Conference,Washington DC,  Sept 15-18 1999, pp. 19-23.

Hierarchy of Signal Interconnect Limits and Opportunities for GSI

1. J. Davis and J. D. Meindl, "Compact Distributed RLC Interconnect Models, Part I - Single line transient, time delay, and overshoot expressions," IEEE Trans. Electron Devices, vol. 47, p. 2068, Nov. 2000.

2. J. Davis and J. D. Meindl, "Compact Distributed RLC Interconnect Models, Part II - Coupled line transient expressions and peak crosstalk in multilevel networks," IEEE Trans. Electron Devices, vol. 47, p. 2078, Nov. 2000

3. J. Davis et al., "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,"Proc. IEEE, vol. 89, pp. 305-324, Mar. 2001.

4. J. Davis, "A Hierarchy of Interconnect Limits and Opportunities for Gigascale Integration (GSI)," Ph. D. Dissertation, 1999, Georgia Institute of Technology.

5. J.A. Davis and J.D. Meindl," Length, Scaling, and Material Dependence of Crosstalk between Distributed RC Interconnects," Proc. IEEE International Interconnect Technology Conference. San Francisco, CA: pp. 227-229, June 1999.

6. J.A. Davis and J.D. Meindl," Compact Distributed RLC Models for Multilevel Interconnect Networks". Symposium on VLSI Circuits, 1999.

7. J. A. Davis and James Meindl, "Is Interconnect the Weak Link?," Circuits and Devices Magazine, March, 1998.

8. J.A. Davis, V.K De, and J.D. Meindl, " A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation," IEEE Transactions on Electron Devices, Vol. 45, No. 3, pp. 590-597, March 1998.

9. J.A. Davis, V.K. De, and J.D. Meindl, "A Stochastic Wire Length Distribution for Gigascale Integration (GSI): Part I: Derivation and Validation," IEEE Transactions on Electron Devices, Vol. 45, No. 3, pp. 580-589, March 1998.

10. J. A. Davis, V. K. De, and J. D. Meindl, "A Stochastic Wire Length Distribution for Gigascale Integration," Proceeding of the Custom Integrated Circuit Conference, May 1997.

11. J.D. Meindl, V.D. De, D.S. Wills, J.C. Eble, X.Tang, J.A. Davis, B. Austin, and A.J. Bhavnagarwala, "Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration," Proceedings of the 1997 IEEE International Solid-State Circuits Conference, ISSCC,pp.232-233, San Francisco, CA, February 1997.

12. J.A. Davis, J.D. Meindl, "Interconnect Limits on Gigascale Integration (GSI)," Materials Research Society, Digest of Technical Papers, Material Research Society Symposium Proceedings, vol. 473, pp. 293-302, 1997.

13. J. A. Davis, J. C. Eble, V. K De, J. D. Meindl, "A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)," Material Research Society Symposium Proceedings, vol. 427, pp. 23-34, 1996.

14. J.C. Eble, V.K. De, J.A. Davis, and J.D. Meindl, "Optimal Multilevel Interconnect Technologies for Gigascale Integration (GSI), 1996 Proceedings of the 13th Annual VLSI Multilevel Interconnnection Conference (VMIC), pp. 40-45, Santa Clara, CA, June 1996.

15. J. A. Davis, V. K. De, J.D. Meindl, "A Priori Wiring Estimations and Optimal Multilevel Wiring Networks for Portable ULSI Systems," Proceeding of 46th Electronic Components and Technology Conference, May 1996, p. 1002-1008.

16. V.K. De, J.C. Eble, D.S. Wills, J. Davis, and J.D. Meindl, "A Generic System Simulator (GENESYS) for Microelectronics Technology and Applicatioins, Proceedings of the Government Amicrocircuit Application Conference (GOMAC'96), pp. 439-442, Orlando, FL, March 1996.

17. J. A. Davis, V. K. De., J. D. Meindl, "Optimal Low Power Interconnect Networks", Digest of Technical Papers of the 1996 Symposium on VLSI Technology, pp. 78-79.

18. J. D. Meindl, J.A. Davis, G. Vish, "A New Metric for GSI," Pico Frontier (Sam Daram), June 1, 1996.

19. J. D. Meindl, J.A. Davis, "Interconnect Performance Limits of Gigascale Integration (GSI)," Materials Chemistry and Physics vol. 41 (1995), pp. 161-166.

Stochastic Interconnect Network Fan-out Distributions for GSI

1. P. Zarkesh-Ha, "Global Interconnect Modeling for a Gigascale System-on-a-Chip (GSoC), " Ph. D. Dissertation, 2001, Georgia Institute of Technology.

2. P. Zarkesh-Ha, J. Davis, and J. D. Meindl, "Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip," IEEE Trans. VLSI Syst., vol. 8, pp. 649-659, Dec. 2000.

3. P. Zarkesh-Ha and J.D. Meindl, "An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC)," Proc. IEEE Symposium on VLSI Technology, June 2000.

4. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, "Prediction of Interconnect Fan-out Distribution Using Rent's Rule," International Workshop on the System-Level Interconnect Prediction, pp. 107-112, April 2000 .

5. P. Zarkesh-Ha and J.D. Meindl, "Asymptotically Zero Power Dissipation Gigahertz Clock Distribution Networks," IEEE Electrical Performance of Electronic Packaging, pp. 57-60, Oct. 1999.

6. P. Zarkesh-Ha, P. Bendix, W. Loh, J. Lee, and J.D. Meindl, "The Impact of Cu/Low k on Chip Performance," to be published in IEEE International ASIC/SoC Conference, Sep. 1999.

7. P. Zarkesh-Ha and J.D. Meindl, "Optimum Chip Clock Distribution Networks," IEEE International Interconnect Technology Conference, pp. 18-20, May 1999.

8. P. Zarkesh-Ha, T. Mule', and J.D. Meindl, "Characterization and Modeling of Clock Skew with Process Variations," IEEE Custom Integrated Circuit Conference, pp. 441-444, May 1999.

9. P. Zarkesh-Ha and J.D. Meindl, "Stochastic Net Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip," IEEE Symposium on VLSI Technology, pp. 44-45, June 1998

10. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, "Stochastic Interconnect Network Fan-out Distribution Using Rent’s Rule," IEEE International Interconnect Technology Conference, pp. 184-186, June 1998

11. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, "On a Pin versus Gate Relationship for Heterogeneous Systems: Heterogeneous Rent's Rule," IEEE Custom Integrated Circuit Conference, pp. 93-96, May 1998

Impact of Extrinsic and Intrinsic Parameter Fluctuations on CMOS Circuit Performance

1. K. A. Bowman, L. Wang, X. Tang, and J. D. Meindl, "A circuit-level perspective of the optimum gate oxide thickness," IEEE Trans. Electr. Devices, vol. 48, pp. 1800-1810, Aug. 2001.

2. K. A. Bowman and J. D. Meindl, "Impact of within-die parameter fluctuations on future maximum clock frequency distributions," Proc. Custom Integrated Circuits Conference, May 2001.

3. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution," Proc., IEEE International Solid State Circuits Conference, Feb. 2001.

4. K. A. Bowman, X. Tang, J. C. Eble, and J. D. Meindl, "Impact of Extrinsic and Intrinsic Parameter Fluctuations on CMOS Circuit Performance," IEEE J. Solid-State Circuits, vol. 35, pp. 1186-1193, Aug. 2000.

5. K. A. Bowman, B. L. Austin, J. C. Eble, Xinghai Tang, and J. D. Meindl, “A Physical Alpha-Power Law MOSFET Model,” Proc. of the 1999 ISLPED, pp. 218-222.

6. X. Tang, K. A. Bowman, J. C. Eble, Vivek K. De, and J. D. Meindl, “Impact of Random Dopant Placement on CMOS Delay and Power Dissipation,” Proc. of the 29th ESSDERC, pp. 184-187, Sept. 1999.

7. K. A. Bowman, Xinghai Tang, J. C. Eble, and J. D. Meindl, “Impact of Extrinsic and Intrinsic Parameter Variations on CMOS System on a Chip Performance,” Proc. of the 12th Annual IEEE Intl. ASIC/SOC Conf., pp. 267-271, Sept. 1999.

8. K. A. Bowman, B. L. Austin, J. C. Eble, Xinghai Tang, and J. D. Meindl, “A Physical Alpha-Power Law MOSFET Model,” IEEE J. Solid-State Circuits, Vol. 34, No. 10, pp. 1410-1414, Oct. 1999.

9. K. A. Bowman, B. L. Austin, X. Tang, and J. D. Meindl, "Complete Power-Delay Analysis for CMOS GSI using a Low Power Transregional MOSFET Model," Techon ’98, Las Vegas, September 8-12, 1998.

10. B. L. Austin, K. A. Bowman, X. Tang, and J. D. Meindl, "A Low Power Transregional Mosfet Model for Complete Power-Delay Analysis of CMOS Gigascale Integration (GSI)," Proceedings of the Eleventh Annual IEEE International ASIC Conference, Rochester NY, pp.125-129, September 13-16, 1998.

Voltage Scaling Limits for CMOS Logic and SRAM Circuits

1. A. Bhavnagarwala, S. Kosonocky, J Meindl, "Interconnect-Centric Array Architectures for Minumum SRAM Access Time", Proc. IEEE International Conference on Computer Design. Austin TX:pp. 352-357, Sept. 2001.

2. Azeez J. Bhavnagarwala, Xinghai Tang, andJames D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability", IEEE Journal  of Solid-State Circuits, Vol. 36, No. 4, April 2001, pp 658-665.

3. A. Bhavnagarwala A. Kapoor and J. Meindl, "Dynamic-threshold CMOS SRAM cells for fast, portable applications " Proceedings of the 13th Annual IEEE International ASIC/SOC Conference. Washington, D.C.:pg. 359-363, Sept. 2000.

4. A.  Bhavnagarwala,  A.  Kapoor  &  J.  Meindl,  "Source Pulsed Dynamic Threshold  CMOS SRAMs for Fast Portable Applications", 26th European Solid State  Circuits  Conference  (ESSCIRC), Stockholm Sweden, September 19-21, 2000, pp. 183-186.

5. A.  Bhavnagarwala,  A.  Kapoor & J Meindl, "Fluctuation Limits on CMOS SRAM  Scaling"  30th  European  Solid  State  Device  Research  Conference (ESSDERC). Cork, Ireland: pp 431-434, Sept. 2000.

6. A. Bhavnagarwala and J. Meindl, "Delay Models for Arbitrary Wire-Tree Networks", TECHCON 2000, September 2000.

7. A. Bhavnagarwala and J. Meindl, "Limits on CMOS SRAM Scaling", TECHCON 2000, September 2000.

8. A. Bhavnagarwala and J. Meindl, "Dynamic Threshold SRAMs for Fast Portable applications" TECHCON 2000, September 2000.

9. A. Bhavnagarwala, A. Kapoor, and J. D. Meindl, "Impact of Interconnect Parameter Variation on Wire-tree Delay" Fifth Int'l Workshop on Statistical Metrology, 2000, pp. 80-83, June 2000.

10. A. Bhavnagarwala, A. Kapoor and J. Meindl, "Generic Models for Interconnect Delay across Arbitrary Wire-Tree Networks", Int'l Interconnect Tech. Conf. 2000, pp.129-131, June 2000.

11. A Bhavnagarwala, B Austin, K Bowman and J Meindl, "A Minimum Total Power Methodology for Projection Limits on CMOS GSI," IEEE Transactions on VLSI Systems, Special issue on Low Power, pp. 235-251, June 2000.

12. A. Bhavnagarwala, B Austin, A. Kapoor and J. Meindl, "CMOS System-On-A-Chip Voltage Scaling beyond 50nm", Proc. of the 10th Great Lakes Symp. on VLSI, pp 7-12, March 2000.

13. A Bhavnagarwala, B Austin, J Meindl, "Minimum Supply Voltage for CMOS GSI", Tech Digest of Papers, Intl Symp on Low Power Elect. & Dsgn, Aug 1998, pp100-102.

14. A Bhavnagarwala, V K De, B Austin, J Meindl, "Circuit Techniques for Low Power CMOS GSI", Digest of Tech Papers, Intl Symp on Low Power Elect & Dsgn, Aug 1996, pp 193-197.

15. A Bhavnagarwala, V K De, B Austin, J Meindl, "Optimal Circuit Design for Low Power CMOS GSI", IEEE Int'l ASIC Conference, Sept 1996, pp 313-316.

16. A Bhavnagarwala, B Austin, J Meindl, "Projections for High Performance Minimum Power CMOS ASIC Technologies: 1998-2010", IEEE Int'l ASIC Conference, Sept 1997 pp 185-188.

17. A Bhavnagarwala, B Austin, J Meindl, "Voltage Scaling Opportunities for CMOS GSI", TECHCON 98, Dig of Tech Papers, pp 1610.

18. J.D. Meindl, J.A. Davis, X. Tang, J.C. Eble, A.J. Bhavnagarawala, and B. Austin, "Intrinsic Limits on Gigascale Integration due to Stochastic Dopant and Interconnect Placement," Proceedings of the Government Microcircuit Application Conference (GOMAC '97), pp. 305-308, Las Vega, NV, March 1997.

19. J.D. Meindl, V.D. De, D.S. Wills, J.C. Eble, X.Tang, J.A. Davis, B. Austin, and A.J. Bhavnagarwala, "Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration," Proceedings of the 1997 IEEE International Solid-State Circuits Conference, ISSCC,pp.232-233, San Francisco, CA, February 1997.

Multi-processor Interconnection Networks

1. C. S. Patel, S. M. Chai, S. Yalamanchili and D. E. Schimmel, Power/Performance Trade-offs for Direct Networks, 2nd Intl. Workshop on Parallel Computer Routing and Communication (PCRCW ’97), Atlanta, Georgia, June 1997.

2. C. S. Patel, S. M. Chai, S. Yalamanchili and D. E. Schimmel, Power Constrained Design of Multiprocessor Interconnection Networks, Proc. IEEE Intl. Conf. on Computer Design: VLSI in Computers and Processors (ICCD ’97), Austin, Texas, 1997.

Modeling and Scaling Limits of Bulk Accumulation and Inversion MOSFET Devices

1. Austin, B.L. Tang, X. Meindl, J.D. Dennen, M. Richards, W.R., "Threshold voltage roll-off model for low power bulk accumulation MOSFETs". Proc Annu IEEE Int ASIC Conf Exhib 1998 IEEE Piscataway NJ USA p 175-179 .

2. B. L. Austin, K. A. Bowman, X. Tang, and J. D. Meindl, "A Low Power Transregional Mosfet Model for Complete Power-Delay Analysis of CMOS Gigascale Integration (GSI)," Proceedings of the Eleventh Annual IEEE International ASIC Conference, Rochester NY, pp.125-129, September 13-16, 1998.

3. A. Bhavnagarwala, B Austin, A. Kapoor and J. Meindl, "CMOS System-On-A-Chip Voltage Scaling beyond 50nm", Proc. of the 10th Great Lakes Symp. on VLSI, pp 7-12, March 2000.

4. R. Murali, B. L. Austin, and J. D. Meindl, "A tick based methodology for rapid predictive circuit modeling," presented at 22002 IEEE International Symposium on Circuits and Systems, 26-29 May 2002, Phoenix-Scottsdale, AZ, USA, 2002.

5. R. Murali, B. L. Austin, L. Wang, and J. D. Meindl, "Scaled accumulation FETs for ultra-low power logic," presented at Proceedings 15th Annual IEEE International ASIC/SOC Conference, 25-28 Sept. 2002, Rochester, NY, USA, 2002.

6. R. Murali, L. Wang, B. L. Austin, and J. D. Meindl, "Low-power circuit advantages of the scaled accumulation FET," presented at 22002 IEEE International Symposium on Circuits and Systems, 26-29 May 2002, Phoenix-Scottsdale, AZ, USA, 2002.

7. R. Murali, B. L. Austin, L. Wang, and J. D. Meindl, "Short-channel modeling of bulk accumulation MOSFETs," IEEE Transactions on Electron Devices, vol. 51, pp. 940-7, 2004.

Random Dopant Fluctuations

1. X. Tang, Ph.D. Dissertation, "Intrinsic and Extrinsic Parameter Fluctuation Limits on Gigascale Integration (GSI)". 1999, Georgia Institute of Technology.

2. A. Bhavnagarwala, X. Tang and J Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability" to be published, IEEE Journal of Solid State Circuits, 2000.

3. K. A. Bowman, Xinghai Tang, J. C. Eble, and J. D. Meindl, “Impact of Extrinsic and Intrinsic Parameter Variations on CMOS System on a Chip Performance,” Proc. of the 12th Annual IEEE Intl. ASIC/SOC Conf., pp. 267-271, Sept. 1999.

4. Xinghai Tang, K. A. Bowman, J. C. Eble, Vivek K. De, and J. D. Meindl, “Impact of Random Dopant Placement on CMOS Delay and Power Dissipation,” Proc. of the 29th ESSDERC, pp. 184-187, Sept. 1999.

5. B.L. Austin, X. Tang, J. D. Meindl, " Threshold Voltage Roll-Off Model for Low Power Bulk Accumulation MOSFETs," Proceedings of the Eleventh Annual IEEE International ASIC Conference, Rochester NY, pp. 175-179, September 13-16, 1998.

6. X. Tang, V. K. De and J. D. Meindl, "Threshold Voltage Fluctuations in GSI MOSFETs", Semiconductor Research Corporation Technical Conference, Techcon'98, Las Vagas, September, 1998.

7. X. Tang, V. K. De and J. D. Meindl, "MOSFET Fluctuation Limits on Gigascale Integration (GSI)," 1998 European Solid-State Device Research Conference (ESSDERC’98), Bordeaux, France, September, 1998

8. X. Tang, V. De, and J. Meindl "Intrinsic and Extrinsic MOSFET Parameter Fluctuation Limits to Gigascale Integration". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 5, pp. 369-376, December, 1997.

9. J. Meindl, V. De, J. Eble, X. Tang, J. Davis, B. Austin, and A. Bhavnagarwala, "The Impact of Stochastic Dopant and Wire Placement on Gigascale Integration", Digest of Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, California, February, 1997.

10. V. De, X. Tang, and J. Meindl "Random MOSFET Parameter Fluctuation limits to Gigascale Integration (GSI)", Digest of Technical Papers, Symposium on VLSI Technology, pp198-199, Honolulu, Hawaii, June 1996.

11. V. De, X. Tang, and J. Meindl, "Scaling Limits of MOSFET Technology Imposed by Random Parameter Fluctuations", Digest of Technical Papers, Device Research Conference, Santa Barbara, California, June, 1996.

12. X. Tang, V. De, and J. Meindl, "Random MOSFET Parameter Fluctuation Effects on Total Power Consumption", Digest of Technical Papers, 1996 International Symposium on Low Power Electronics and Design, pp 233-236, Monterey, California, August, 1996.

13. X. Tang, V. De, and J. Meindl, "Random dopant placement limits to Gigascale Integration (GSI)", Semiconductor Research Corporation Technical Conference, Techcon'96, Phoenix, Arizona, September, 1996.

14. X. Tang, V. De, and J. Meindl, "Intrinsic Dopant Fluctuation Imposed Limitations on Gigascale Integration (GSI)" Proceedings of SEMI Beijing Conference, Beijing, P. R. China, November, 1996.