Calvin King  

Bio
Calvin King graduated summa cum laude with a Bachelor of Science degree in Electrical Engineering from Tennessee State University in May of 2005.  As an undergraduate, he pursued research in the area of Computer and Information Systems Engineering. He held the distinction of Coca-Cola National Scholar and received various awards including TSU Department of Electrical and Computer Engineering Most Outstanding Senior. During the summers of 2003-05, he interned with the Systems and Technology Group at the IBM Corporation.
He is currently a Semiconductor Research Corporation (SRC)/IBM PhD Fellow and a Facilitating Academic Careers in Engineering and Science (FACES) PhD Fellow.  Mr. King’s research interest is “3D Nanosystem Integration Using Electrical, Optical, and Fluidic Interconnects.”

Research Description

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Gerald Lopez

Bio
Gerald Lopez graduated cum laude with a Bachelor of Science degree in Computer Engineering from the University of Maryland, Baltimore County in December 2001 as a Meyerhoff Scholar. Immediately following, he joined the GSI group in January 2002. In July 2004, he received his Masters from the School of Electrical and Computer Engineering here at the Georgia Institute of Technology. He has interned with IBM Corporation at the T.J. Watson Lab in Yorktown Heights, New York.

Research Description
His current research interest involves the investigation of interconnect process variations and their impact on future GSI chip performance.

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Ramasamy Ravindran  

Bio
Ramasamy received his Bachelor of Science and Master of Science degrees in Electrical Engineering from the University of Missouri-Columbia in 2004 and 2006 respectively. His Masters research was on nanocomposite high-k dielectrics with embedded metal nanoparticles.

Research Description
He is currently working in collaboration with the Department of Biology on a bio-sensors project.

Reza Sarvari

Bio
Reza Sarvari was born in Mashad, Iran in 1974. He received the B.S. and M.S. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran in 1996, and 1998 respectively. He received the M.S. in electrical and computer engineering from Georgia Institute of Technology (Georgia Tech), Atlanta, in 2003 where he is pursuing his PhD.

Research Description
His current research interests are in the areas of interconnect modeling, high frequency and size effects (line anomalous skin effect, and surface scattering) in electrical interconnects.

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Deepak Sekar

Bio
Deepak was born in Vellore, India in 1982. He received a B. Tech from the Indian Institute of Technology (Madras) in 2003 and a M.S from Georgia Tech in 2005, both in Electrical and Computer Engineering. He is currently pursuing a PhD at Georgia Tech.

Deepak interned in IBM’s clock distribution group in Summer 2004. He joined SanDisk Inc. as a Member of Technical Staff in Fall 2006, and is now on leave from SanDisk to complete his PhD studies. While at SanDisk, Deepak worked on NAND flash memory device and circuit design. 

Some of the awards he has received include the Intel PhD Fellowship, the Maharashtra State Government Fellowship for undergraduate studies and the National Talent Search Scholarship given by the Govt. of India. His research interests span VLSI technology, device physics, interconnects, packaging, low-power circuits and VLSI system design. Deepak has ten patents pending and has authored several publications.

Research Description
Interconnects (wires) play a vital role in deciding the total system performance of a sub-50nm integrated circuit. Wires can be classified into four types based on the function they perform:

• Signal interconnects → Transport signals from one transistor to another
• Power interconnects → Deliver power to the integrated circuit
• Clock interconnects → Supply a clock signal to all the flip-flops and latches
• Thermal interconnects → Heat removal

The objective of this research is to find ways to significantly enhance the performance of these four types of interconnect networks and to co-design them using a system-level simulator.

Resume

James Yang

Bio
James Yang received B.S in Computer Engineering with High Honor and M.S. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2007 and 2008, respectively. In 2009, he joined Gigascale Integration (GSI) group led by Dr. James Meindl and Dr. Muhannad Bakir, as a graduate research assistant pursuing Ph.D.

He was born in South Korea and grew up in Wollongong, Australia before coming to United States.

His hobbies include skiing, skydiving, dancing (argentina tango and salsa) and meeting new people.

Research Description

• MEMS industry is projected to become a $11.5B industry by 2011.
• Number of MEMS devices available are increasing and fabrication techniques/materials used are diversifying rapidly.
• Conventional integration strategies are becoming obsolete and are unable to keep up with demand for:
  • increased compatibility with new materials /processes
  • higher performance (electrical and mechanical)
  • higher I/O density
  • shorter time-to-market
  • lower cost solutions

My research aims to address above demands through the use of novel compliant interconnects and through-silicon-vias, thereby enabling the integration of a state-of-the-art CMOS process with an arbitrary MEMS process.

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Farhana Zaman

Bio
Farhana Zaman was born in Dhaka, Bangladesh. She spent most of her school-years in Kuwait.  In order to pursue her B.S. degree in Electrical Engineering, she came to Georgia Institute of Technology in 2000. Upon completing her undergraduate studies in 2004, Farhana went on to receive her M.S. degree in Electrical and Computer Engineering in 2006.  She is currently working towards a Ph.D. degree in Electrical and Computer Engineering with a minor in Materials Science and Engineering. Farhana is a student member of IEEE and Eta Kappa Nu.  She was also awarded the TI Graduate Woman’s Fellowship for Leadership in Microelectronics.   

Research Description
Current CMOS technology for the fabrication of transistors has reached its theoretical limits. In order to continue scaling according to the ITRS predictions, post-CMOS methodologies need to be realized. Some of the possible solutions are looking into alternative computational state variables other than electron charge, and investigating novel energy transfer mechanisms, such as spin waves, orbitron waves, and plasmon waveguides.  To achieve successful results in this area, Farhana is looking into developing a novel nano-transistor using the electron beam lithography system.  She is also fabricating sub-5nm electrode gaps useful for molecular electronics and single molecule detection. 

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