Adder transistor sizing
You will use the Spice to determine transistor sizes for a 16-bit ripple-carry adder.
You should turn in:
- Answers to prelab questions.
- The schematic of the circuit you simulated.
- Plots and measurements.
Draw a transistor schematic for a full adder cell using static, complementary gates.
Using a transistor-level schematic of a two-bit adder based on your full adder cell, identify the critical path for a two-bit adder.
Things you need to do for the lab:
- Build a hierarchical schematic for the adder.
- Simulate the adder.
- Determine transistor sizes for the cells.
Hierarchical adder schematic
Draw a schematic for a one-bit full adder based on your pre-lab design. Use minimum sizes for all transistors. Simulate the one-bit design to be sure it works.
Use the one-bit adder as a cell to create a four-bit ripple-carry adder cell. Then use the four-bit cell to create a 16-bit adder.
Simulate the 16-bit adder
Simulate the 16-bit adder using Spice. Determine the worst-case delay.
Determine transistor sizes
Modify the schematic to create two versions of the one-bit cell: one with all transistors minimum-size and one with critical path transistors that are twice minimum size. Create a four-bit adder that uses the larger-size transistors in all four bits. Create two versions of the 16-bit adder: one that uses the larger transistors only in the bottom four bits; and one that uses the larger transistors in all 16 bits.
Simulate the worst-case delay of both adders. Compare the delays to each other and to the all-minimum-size adder.