People

Nawaf Almoosa

Nawaf's main interest is understanding the behavior of complex systems, which arise in various engineering, biological and social environments. His Ph.D. work In CASL involves applying formal methodologies used in other engineering disciplines to the modeling and optimization of computing systems. His research interests, in addition to computer architecture, include signal processing, operations research, and control theory.
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Dhruv Choudhary

Dhruv is an MS student at Georgia Tech. His research focus is on developing micro-architectural and compiler optimizations for interconnects and memory hierarchy specially in heterogeneous and chip-multiprocessor architectures. Power optimization and energy efficiency for interconnection networks are some of his primary concerns.
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Gregory Diamos

Gregory Diamos is a PhD student in the Computer Architecture and Systems Lab at the Georgia Institute of Technology, under the direction of Professor Sudhakar Yalamanchili. He received his B.S. and M.S. in Electrical Engineering from the Georgia Institute of Technology in 2006 and 2008, respectively, where he focused on architecture techniques for controlling PVT variations. His current research interests follow the industry shift from ILP to many core architectures, where mounting communication requirements place increasing demands on on-chip interconnection and the ability to tightly integrate heterogeneous architectures offers the potential for dramatic improvements in efficiency at the cost of increased design complexity; his research is directed toward maintaining this efficiency while reducing design complexity.
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Syed Minhaj Hassan

Minhaj is a Ph.D student at Georgia Tech in Computer Architecture & Systems Laboratory (CASL). His current research focus is on memory controller optimizations for multicores and future many-core systems. Overall, he is interested in micro-architecture techniques for improving area/power/performance in specific domains like computer atchitecture, digital signal processing & communications.
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Andrew Kerr

Andrew's attention first turned to computer architecture because he wanted his 3D graphics programs to run faster. Since recognizing the coupling between architecture, compilation tools, programming languages, and software design, Andrew has pursued this interest at Georgia Tech, earning both a bachelor's and a master's in computer engineering from the School of ECE. He is currently a PhD student focusing on the productivity challenges posed by heterogeneous multicore compute architectures.
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GPU VSIPL
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Chad Kersey

Chad is a Ph.D. student currently working on parallel multicore simulations of computer architectures built with CPU emulators and parallel discrete event simulation frameworks. His research interests include offload of computation to the memory hierarchy and improvements in the design of simulators for computer architecture. Chad's hobbies include the preservation and dissemination of computing history, both out of appreciation for historic feats of engineering and nostalgia for the family Commodore 64.
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Si Li

Si Li is a PhD student at Georgia Tech working in the area of computer architecture. His research interests involve the unique demand of memory and cache systems in the massively parallel environment of general purpose GPU architecture. His other interests include power and performance in the domain of computer architecture.
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Sharda Murthi

Sharda Murthi is a Masters student working on the Manifold project under the direction of Prof. Yalamancili.


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Mitchelle Rasquinha

Mitchelle Rasquinha is a masters student at Georgia Tech working in the area of computer architecture. Her research interests are centered on micro-architecture optimizations to memory systems in the current era of multicore architectures. She is currently involved in studying memory controller optimizations for systems supporting large data set applications.
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William Song

William Song is a Ph.D student with research focuses on power, temperature, and packaging reliability modeling, measurement, and management of heterogeneous multicore processors. His interests include evaluation of cooling, cost, space, energy, and performance tradeoffs.
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Dr. Sudhakar Yalamanchili

Sudhakar Yalamanchili earned his PhD degree in Electrical and Computer Engineering in 1984 from the University of Texas at Austin after which he joined Honeywell’s Systems and Research Center in Minneapolis where he worked as a Senior, and then Principal Research Scientist from 1984 to 1989. In both capacities, he served as the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. While at Honeywell, Dr. Yalamanchili also served as an Adjunct Faculty and taught in the Department of Electrical Engineering at the University of Minnesota. He joined the ECE faculty at Georgia Tech in 1989 where he is now a Joseph M. Pettit Professor of Computer Engineering. He has served as the PI and Co­PI on sponsored projects in the areas of reconfigurable computing, high performance interconnection networks, and resource management for parallel architectures. He is the author of VHDL Starters Guide, 2nd edition, Prentice Hall 2004, VHDL: From Simulation to Synthesis, Prentice Hall, 2000, and co­author with J. Duato and L. Ni, of Interconnection Networks: An Engineering Approach, Morgan Kaufman, 2003.
Dr. Yalamanchili is a Senior Member of the IEEE. He has served as a Distinguished Visitor of the IEEE, and associate editor for the IEEE Transactions on Parallel and Distributed Processing and IEEE Transactions on Computers. He contributes professionally through service on conference and workshop program committees in the area of high performance computing, computer architecture, and interconnection networks.
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Jeffrey Young

Jeff is a Ph.D student at Georgia Tech working in the area of computer architecture. His research emphasis is developing novel interconnects and memory systems for next-generation multicore and heterogeneous processors. His other interests include traditional networking, computer and network security, and using reconfigurable logic for high performance computing.
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