Georgia Tech > CoE > ECE > CASL
People
- Gregory Diamos
- Vikas Doshi
- Elizabeth Lynch
- Arun Rodrigues (DOE)
- George Riley
- Sudhakar Yalamanchili
People
- Chad Kersey
- Vishakha Gupta
- Jose Duato
- Sudhakar Yalamanchili
Multicore Infrastructure & Tools
The evolution to multicore architectures has left a void in accurate systems simulation that cannot be met by traditional point tools such as standalone microarchitecture simulators and interconnection network simulators. Integrated simulation environments are too slow for high fidelity simulations. While high fidelity emulation environments such as RAMP are ultimately desirable, we seek a mid-point between sequential environments and hardware emulators met with coarse grain distributed simulation. Such environments can enable rapid exploration architectural design spaces as a prelude to hardware emulation and FPGA based acceleration. Towards this end we are working on two infrastructures: CAPSTONE and Multi-Cell Simulator.
CAPSTONE
CAPSTONE is a cycle accurate distributed simulation environment for interconnection networks. The simulator kernel is an parallel adaptation of the structured simulation toolkit (SST) from Notre Dame/DOE. The longer term vision is the integration of CAPSTONE with microarchitectural simulators such as SIMICS and PTLSIM and with DRAM simulators such as DRAMSim to produce a coarse grain, distributed simulation environment. We are currently in the process of testing CAPSTONE on the large scale machines at Oakridge National Laboratories. CAPSTONE also includes some (basic) tools for dependence visualization, automated route table construction for source routing, and topology generation and visualization.
Project Documentation
The papers are provided for personal use and are subject to copyright of the publishers
Source code
Multi-Cell Simulator (MCS)
The need for exploring multi-cell architectures requires an environment for generating and running parallel code on multiple interconnected CellBE processors. MCS is a distributed simulation environment for modeling multiple, communicating Cell/BE processors using IBM’s MAMBO cell simulator. MCS currently enables multiple simulator instances to communicate, serving the modeling of multi-cell architectures. MCS further supports i) a pooled accelerator execution model for orchestrating computations on and data movements across multiple cell problem, and ii) an API for transparently implementing effective movement of data and control information across multiple elements. The size of the multi-cell system that can be simulated and supported by the execution model is only limited by number of physical cores available to host parallel instances of the Cell simulator. The current version utilizes only functional inter-cell communication via sockets. Future versions will port the communication layer to the CAPSTONE cycle level network simulator to explore a range of multi-cell topologies and architectures and their interaction with applications.
Project Documentation
The papers are provided for personal use and are subject to copyright of the publishers
Multi-Core Simulator and QEMU
There is a beginning effort devoted creating a multi-core emulator that is capable of emulating future many-core architectures. Currently, the only existing documentation is a QEMU internals overview given by Chad Kersey to the GT Linux Users Group.
