Georgia Tech > CoE > ECE > CASL
People
- Nawaf Alamoosa
- Jeffrey Young
- Jose Duato
- Federico Silla
- Yorai Wardi
- Sudhakar Yalamanchili
Former Students
- Subramanian Ramaswamy
High Efficiency Computing
This theme is motivated by several trends including i) rising importance of on-chip interconnection structures between cores and within the cache memory system, ii) the narrowing of the latency gap between DRAM access and inter-socket/inter-board interconnects, and iii) rigid policies for memory and interconnect operation. This theme initially seeks to identify and mitigate inherent efficiencies in current architectural structures via hardware enhancements and accompanying software structures for off-line and on-line customization of architectural attributes to improve performance and energy efficiency.
On-chip we are addressing management of cache resources and interconnects while off-chip we are exploring implementation and management of large 64-bit physical memory spaces. Memory-to-memory latency is a critical performance determinant of scalable computing systems. The use of modern interconnect fabrics tightly coupled to the processor-memory hierarchy such as AMD’s HyperTransportTM (HT) and Intel’s Quickpath (QPI) have the potential to provide the lowest end-to-end transfer latency for systems comprised of tens to thousands of multicore nodes. However, to productively harness this raw capability, it must be exercised in the context of a global system model that defines how the system wide address space is deployed and utilized. Towards this end we advocate and explore the implications, architectural support and implementation of a Dynamic Partitioned Global Address Space (DPGAS) model for the implementation of scalable cluster systems. A prototype implementation based on HT-Over-Ethernet (HToE) is being developed that is suitable for experimentation and measurement. In particular, we are concerned about the portability of the model and software implementations across future generations of processors with increasing physical address ranges focusing on non-coherent address spaces with region based memory semantics where coherency is an application specific, customizable attribute.
Sponsor: National Science Foundation.
Presentations
- J. Young, S. Yalamanchili, "Dynamic Partitioned Global Address Spaces for Improving Memory Efficiency" CERCS presentation, December, 2008
- J. Young, S. Yalamanchili, F. Silla, and J.Duato, "A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency", presented at WHTRA, Feb. 2009.
Papers
The papers are provided for personal use and are subject to copyright of the publishers
- J. Young, S. Yalamanchili, F. Silla, and J.Duato, "A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency", WHTRA, Feb. 2009.
- S. Yalamanchili, J. Young, J. Duato, and F. Silla, “A Dynamic Partitioned Global Address Space Model for High Performance Cluster,” Technical Report:GIT-CERCS-08-01, School of Electrical and Computer Engineering, Georgia Tech, January 2008.
- S. Yalamanchili, R. Ramaswamy, and G. Diamos, "From Adaptive to Self Tuned Systems," Proceedings of the Stammatis Vassiliadis Sympoisum on the Future of Computing, September 2007.
- S. Ramaswamy and S. Yalamanchili, “Improving Cache Efficiency via Resizing + Remapping,” Proceedings of the IEEE International Conference on Computer Design, October 2007.
- G. Diamos, S. Yalamanchili. J. Duato, “STARS: A System for Tuning and Actively Reconfiguring Links," Poster: Workshop on Diagnostic Services in Network on Chips, held with Design and Test Europe, April 2007.
- S. Ramaswamy and S. Yalamanchili, “Customized Placement for Embedded Processor Caches,”, Proceedings of Architecture of Computing Systems, March 2007.
- S. Ramaswamy and S. Yalamanchili, “Customizable Fault Tolerant Caches for Embedded Processors,” Proceedings of the IEEE International Conference on Computer Design, October 2006.
- S. Ramaswamy, J. Sreeram, S., Yalamanchili, K. Palem, “Data Trace Cache: An Application Specific Cache Architecture,” Proceedings of the ACM Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, August 2005.
Theses and Dissertations
- Subramanian Ramaswamy, "Active Management of Cache Resources" PhD Dissertation, July 2008.
- Jeffrey Young, "Dynamic Partitioned Global Address Spaces for High-Efficiency Computing" Masters Thesis, December 2008.
