Faculty Profile - Linda S Milor
Office: Klaus 1354
Selected Publications, Patents
- M. Orshansky, L. Milor, and C. Hu, "Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level cirrection," IEEE Trans. Semiconductor Manufacutring, vol. 17, no. 1, pp. 2-11, Feb. 2004.
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Computer-Aided Design, vol. 21, no. 5, pp. 544-553, May 2002.
- L. Milor, "A tutorial introduction to analog and mixed-signal testing," IEEE Trans. Circuits and Systems II, vol. 45, no. 10, pp. 1389-1407, Oct. 1998.
- C.Y. Chao, H-J. Lin, and L. Milor, "Optimal testing of VLSI analog circuits," IEEE Trans. Computer-Aided Design, vol 16, no. 1, pp. 58-77, Jan. 1997.
- L. Milor and A. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Trans. Computer-Aided Design, vol. 13, no. 6, pp. 796-813, June 1994.
- L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Computer-Aided Design, vol. 8, no. 2, pp. 114-130, Feb. 1989.
Last revised on June 06, 2008.