ECE3055 - Computer Architecture and Operating Systems

Instructor

Dr. George F. Riley
Office: CoC 351
Office hours: MWF 11-12 and MWF 2-3pm in CoC 351
Email: riley@ece.gatech.edu

Course Summary

ECE3055 is designed to give students a detailed understanding of computer architecture, and a basic understanding of the functions and design of computer operating systems. The hardware architecture portion of the class focuses on the MIPS chip design and implementation, which are discussed in detail. However, the principles covered are applicable to most modern architectures. The operating systems portion of the class discusses basic functions that must be provided by all operating systems, without covering any one specific OS in detail.

Teaching Philosophy

The class web page will give an description of the material for each lecture. The class lectures will cover the material in a discussion format, where the instructor will explain how things are done, and then we will discuss in detail why things are done in certain ways. I encourage (and expect) you to participate actively in the learning process. In particular, I welcome your comments and questions as we cover material in class. One-way lectures quickly becoming boring, both for you and for me. Also, I have found that students often learn more from other students comments than from the instructor! By asking lots of questions, your understanding of the material will be deepened significantly, and the course will be much more fun!

Teaching/Learning Goals

The purpose of this course is for you to understand the fundamentals of what is happening in inside a computer when you as a computer user ask the computer to do something for you. Very few of us will actually design or implement an computer system in our careers, but a good solid understanding of what is going on inside the computer is invaluable in overall system design. In particular, we will learn and understand (at a minimum):

Instruction Set Architecture
Pipelined Data Paths
Memory Hierarchy
Virtual Memory
Process Management
Thread Management
Synchronization
Operating System Functions
Kernel/User Boundaries
Input/Output

Textbooks (Required)

Computer Organization and Design, The Hardware and Software Interface, 2nd ed., D. Patterson and J. Hennessy, ISBN 1-55860-428-6
Operating System Concepts with Java, A. Silberschatz, P. Galvin, and G. Gagne, ISBN 0-471-48905-0
texts will be supplemented with class notes

Getting Help

There will be four teaching assistant for this course. They will do all grading of lab projects and should be your first point of contact when you have questions about assignments or grading.

Teaching Assistant: Weilai Yang gte237t@prism
Lab hours: See below
Teaching Assistant: Sudarshan Srinivasan gtg532c@prism
Lab hours: See below
Teaching Assistant: Mario Vittes gte014w@prism
Lab hours: TBD

TA Office Hours

The office hours for the 3055 Teaching Assistants will be in the ECE computer labs on third floor of College of Computing. Hours for each TA are in the table below.

Mon Tue Wed Thu Fri

10-11 AM

11-12 PM

12-1 PM WY

1-2 PM WY

WY

2-3 PM MV WY MV WY MV

3-4 PM MV WY MV WY MV

4-5 PM MV WY MV WY MV

5-6 PM

MV WY

6-7 PM SS SS SS

7-8 PM SS SS SS

8-9 PM SS SS SS

Grading

Six Projects (Project 5 counts DOUBLE!)	36%
Midterm 1	15%
Midterm 2	15%
Final	24%
Class Participation	10%
Total	100%

Syllabus

Day	Month	Date	Topic	Reading
Mon	Jan	5	Introduction, Overview, Instruction Set Architecture	PH, Ch1 and Ch3
Wed	Jan	7	Instruction Set Architecture (cont)	PH Ch3
Fri	Jan	9	Using the SPIM MIPS simulator
			SPIM, the MIPS Simulator (Linux Source)
			SPIM, the MIPS Simulator (Windows Zip File)
			MIPS Instruction Summary
			Sample SPIM/MIPS Program
Mon	Jan	12	Design of a simple ALU	PH, Sec 4.5, pp 230-241
			Project 1 Assigned
			Project 1 Skeleton Program
			Project 1 Expected Results
			Project 1 Expected Results (Better)
			Project 1, Solution with only one branch
Wed	Jan	14	Single Cycle Datapath	PH, Sec 5, pp 338-372
			Interesting Reading, Pentium Floating Point Divide Bug	PH, Sec 4.10 pp 305(last para)-308
Fri	Jan	16	Multi-Cycle Datapath	PH, Sec 5, pp 377-398
Mon	Jan	19	HOLIDAY! No Class
Wed	Jan	21	INSTRUCTOR OUT OF TOWN! No Class
Fri	Jan	23	Pipelining	PH, pp434-504
			Lab2 Assignment
			Lab2 VHDL Files
			Lab2 VHDL Files (revised)
Mon	Jan	26	Pipelining (continued)
Wed	Jan	28	Memory	PH pp 540 - 579
Fri	Jan	30	Memory (continued)
Memory	Feb	2	Holiday. No Class
Wed	Feb	4	Memory
Fri	Feb	6	Memory
Mon	Feb	9	LAB Assignment 2 DUE
Wed	Feb	11	MIDTERM EXAM 1
Fri	Feb	13	Memory
Mon	Feb	16	Virtual Memory
			Lab3 Assignment
			program-data-hazard.mifMIF file for part 1 program
			program-branch-hazard.mifMIF file for part 2 program
			Lab2 Solution, for Lab 3 starting point
Wed	Feb	18	Virtual Memory
Fri	Feb	20	Virtual Memory (continued)
Mon	Feb	23	Operating Systems Overview	Silberschatz-Galvin, Ch 1
Wed	Feb	25	Operating Systems Overview (continued)	Silberschatz-Galvin, Ch 2
Fri	Feb	27	Operating Systems Overview (continued)	Silberschatz-Galvin, Ch 3
Mon	Mar	1	Threads and Thread Synchronization testpt0.c testpt1.c testpt2.c
Wed	Mar	3	Threads and Thread Synchronization (continued)	Silberschatz-Galvin, Ch 4 and 5
Fri	Mar	5	Threads and Thread Synchronization (continued)
Mon	Mar	8	SPRING BREAK!
Wed	Mar	10	SPRING BREAK!
Fri	Mar	12	SPRING BREAK!
Mon	Mar	15	Lab4 Assignment	Silberschatz-Galvin, Ch 7, pps 239-241
			dining-c.tar.gz
			dining-java.tar.gz
Wed	Mar	17	Synchronization Algorithms	Silberschatz and Galvin, Chapter 7
Fri	Mar	19	Leslie Lamport's Bakery Algorithm
			Sample Java Threads Program Testjt0.java Philosopher.java
Mon	Mar	22	Barriers BuggyBarrier BuggyBarrier2 Sense-Reversing Barrier
Wed	Mar	24	Midterm Exam Review
Fri	Mar	26	MIDTERM EXAM 2
Mon	Mar	29	File Systems
Wed	Mar	31	File Systems Continued
Fri	Apr	2	Lab 5/6 Assigned Due April 18, 2003
			lab5.tar.gz
			lab5-java.tar.gz
Mon	Apr	5	File Systems Continued
Wed	Apr	7	File Systems Continued
			Java Byte Array Conversion
			Java Directory Entry class
Fri	Apr	17	Input-Output Systems	Silberschatz and Galvin, Chapter 12
Mon	Apr	19	Managing Secondary Storage	Silberschatz and Galvin, Chapter 14
Wed	Apr	21	The Banker's Algorithm	Silberschatz and Galvin, Chapter 8, pp 299 - 303
Fri	Apr	23	FINAL EXAM REVIEW

Grades

Student ID (anonymous)	Participation	Lab 1	Lab 2	Lab 3	Lab 4	Lab 5	Lab 6	Midterm 1	Midterm 2	Final Exam	Final Avg	Grade
1	2	8	0	6.4	7	0		69	70	81	55.1	D
2	5	0	9	10	10	10		68	85	87	78.2	B
3	2	6	0	0	0	0
4	10	10	10	10	8	9.4		93	105	90	95.4	A
5	10	10	7	9	9	9		70	105	90	89.7	A
6	6	10	10	10	10	9.4		92	85	93	90.2	A
7	10	10	9	10	10.4	10		99	105	88	97.4	A
8	6	9	0	0	0	0		15	50	46	32.2	F
9	10	10	7	10	10	10		68	98	95	91.9	A
10	8	4.5	7	9	8	10		93	100	95	88.9	A
11	0	9	3.5	4	7	1.6		76	80	73	56.9	D
12	10	12	5	10	11	10		90	105	95	96.9	A
13	10	10	6	5	10	0		85	75	63	67.7	C
14	10	10	9	7	10	10		97	105	99	97.7	A
15	10	10	6.4	10	0	1		73	95	87	73.1	C
16	9	10	10	8.5	0	5		95	100	72	78.6	B
17	5	10	1	0	4	1		52	75	46	45.3	F
18	10	9	7	7	9	10		87	94	93	90.7	A
19	9	10	8	9	10	10		74	100	84	89.5	A
20	10	10	0	0	9	9.6		73	105	76	77.9	B
21	10	10	5.4	7	10	5		93	105	100	89.1	A
22	8	9	3	6	0	10		56	85	83	71.9	C
23	10	11	10	10	10	6.4		64	100	84	87.0	B
24	10	9	10	9	10	9.4		93	80	63	85.2	B
25	10	9	6.5	9.5	10	6		93	100	79	86.1	B
26	10	10	10	10	9.75	10		100	100	94	98.4	A
27	10	9	10	10	9	9.4		92	105	99	97.4	A
28	10	9	2	0	0	8		69	65	82	66.0	C
29	10	12	8	10	11	11		92	100	92	98.7	A
30	10	10	7	9.5	10	6		71	100	92	86.8	B

Contact Information:

riley@ece.gatech.edu

School of Electrical and Computer Computing

Georgia Institute of Technology

Atlanta, GA 30332-0250

	Mon	Tue	Wed	Thu	Fri
10-11 AM
11-12 PM
12-1 PM	WY
1-2 PM	WY			WY
2-3 PM	MV	WY	MV	WY	MV
3-4 PM	MV	WY	MV	WY	MV
4-5 PM	MV	WY	MV	WY	MV
5-6 PM			MV	WY
6-7 PM	SS	SS	SS
7-8 PM	SS	SS	SS
8-9 PM	SS	SS	SS