Xilinx Resource Page

This is a collection of projects, laboratory exercises, and useful VHDL modules for Xilinx's FPGAs. The Cooperative Analog/Digital Signal Processing Laboratory is run by Professor David V. Anderson, and this web page is maintained by one of his graduate students, Tyson S. Hall.

ECE 4273 Laboratory Assignments

The followings labs were used in the DSP Chip Design class at Georgia Tech in Fall 2002. They are designed for use with Digilent's Digilab-IIE board. This is a low-cost FPGA board with a 200K-gate Spartan-IIE chip on it that is available from www.digilentinc.com.

•   Xilinx ISE Tutorial

This is a step-by-step tutorial that introduces you to the basic functionality of Xilinx's ISE 4.2i software.

•   VHDL Implementations (support files)

This lab steps you through the development of a VHDL module to control an LCD display.

•   Buffering and Fixed-Point Arithmetic (support files)

This lab introduces you to the basic concepts of circular buffering and fixed-point math. Additionally, it introduces the Matlab-FPGA interface that has been developed at Georgia Tech's Cooperative Analog/Digital Signal Processing Laboratory to aid in the debugging and analysis of hardware DSP systems.

•   FIR Filtering and the CADSP Audio Interface (support files)

This laboratory will introduce you to the basic concepts of ¯xed-point multiplication, Coregen IP cores, and FIR ¯lters. Additionally, you will be using an audio daughter card for the Digilab-IIE board that has been developed at Georgia Tech's Cooperative Analog/Digital Signal Processing Laboratory to aid in auditory and real-time analysis of DSP systems.

•   Optimization Techniques for FIR Filters (suppport files)

This lab introduces you to some of the basic optimization techniques for FIR filters.

•   Distributed Arithmetic Implementations

This laboratory introduces you to the Distributed Arithmetic method of filter implementation. This is a very area-effecient design technique for implementing filters, transforms, and more on FPGAs.

•   Floating-point Unit (files)

This laboratory explores the use of floating-point numbers and operators. A floating-point co-processor will be developed as an add-on unit for a general-purpose RISC microprocessor. Additionally, an adaptive filter will be implemented in software that will run on the resulting floating-point processor. Note: The MIPS files in this archive are still formatted for the Altera MAX+PLUS II software. This software was used for this laboratory because of its easy-to-use simulator.

Xilinx versions of UP1core modules

These modules were first introduced for the Altera UP development board in Rapid Prototyping of Digital Systems by James O. Hamblen and Michael D. Furman. While the VHDL code works similarly on the Altera and Xilinx FPGAs, there are some minor differences in syntax checking. In addition, the IP cores that use Altera's Library of Parameterized Modules (LPM) for implementing the memory must be changed to use Xilinx's Coregen memory modules.

• UP1core.zip - archive of all the UP1core files
• char_rom.zip - Character generator for VGA display (includes character ROM as Coregen distributed memory block)
• clk_div.vhd - Clock divider module
• debounce.vhd - Debounce module for pushbuttons
• dec_7seg.vhd - Seven-segment display driver
• keyboard.vhd - PS/2 keyboard module
• mouse.vhd - PS/2 mouse module
• onepulse.vhd - Single pulse module
• vga_sync.vhd - Generates the VGA synchronization signals (horizontal and vertical sync pulses)

Xilinx version of simple computer

This simple soft-core processor was first introduced for the Altera UP development board in Rapid Prototyping of Digital Systems by James O. Hamblen and Michael D. Furman. While the VHDL code works similarly on the Altera and Xilinx FPGAs, there are some minor differences in syntax checking. In addition, the IP cores that use Altera's Library of Parameterized Modules (LPM) for implementing the memory must be changed to use Xilinx's Coregen memory modules.

• Coming Soon...

Xilinx version of MIPS computer

This VHDL implementation of a soft-core MIPS procssor was first introduced for the Altera UP development board in Rapid Prototyping of Digital Systems by James O. Hamblen and Michael D. Furman. While the VHDL code works similarly on the Altera and Xilinx FPGAs, there are some minor differences in syntax checking. In addition, the IP cores that use Altera's Library of Parameterized Modules (LPM) for implementing the memory must be changed to use Xilinx's Coregen memory modules.

• Coming Soon...

DSP Workshop Paper

The Matlab-FPGA interface is used throughout the ECE 4273 course at Georgia Tech. It allows students to explore real-world problems and hardware implementations, while analyzing them in a very familiar software environment (i.e., Matlab). To introduce this concept in DSP education, Tyson Hall and Dr. David Anderson presented a paper about this interface at the IEEE Signal Processing Society's 2nd Signal Processing Education Workshop at Pine Mountain, GA in September 2002.

Simulating...