ECE 4100/6100
Advanced Computer Architecture


Prerequisites
: ECE 3055

Catalog Description: Comprehensive coverage of the architecture and system issues that confront the design of high performance workstation/PC computer architectures with emphasis on quantitative evaluation. Credit is not allowed for both ECE 6100 and any of the following courses: ECE 4100, CS 4290, and CS 6290.

Course Syllabus: http://www.ece.gatech.edu/academics/courses/course_outline.php?prmCourse=ECE6100



Instructor:

Sudhakar Yalamanchili

Teaching Assistant:

Contact Information:

Office Hours:

Dean Lewis

Email: dean@gatech.edu

TR 1:30 PM – 3:30 PM
College of Computing (CoC) 309



Contact Information:

Technology Square Research Building (TSRB) 438
Tel: 404-894-2940
Email: sudha@ece.gatech.edu



Office Hours:

MWF 11:00 AM – 12:55 PM
College of Computing (CoC) 348
Tel: 404-894-6877







Class:

MWF 1:05 PM – 1:55 PM
Van Leer (VL) W200



Grading:

Exam I – 15%
Exam II – 15%
Final – 30%
Assignments – 40%



Exam Schedule:

Exam I – Friday, September 22nd, 2006
Exam II – Friday November 2nd, 2006
Final Exam – Thursday, December 14th, 2:50-5:40

Exam I Solutions
Exam II Solutions



Assignment Schedule:

Assignment 1 (Updated 9/22/06)


Assignment 2 (Posted 10/13/06)


Assignment 3 (Updated 11/13/06)


Assignment 4 (Posted 11/30/06)



Laboratory:

Directions for laboratory portions of assignments


Submission Guidelines







Lectures:
Note that PDF versions of papers may be provided as a convenience for private educational use and are subject to copyright restrictions noted on the documents.

Module

Topic

Reading Assignment

Notes

1

Overview and ILP Taxonomy


Moore’s Law
ITRS Road Map

2

Overview: Optimizing Compilers



3

Hardware Scheduling: Part I
Hardware Scheduling: Part II

A Great Example from UC Berkeley*

Sample Problems: Dependencies
Sample Problems:HW Scheduling

4

Branch Prediction
Performance Evaluation

Trace Cache
Intel P4
Power 5

Sample Problems: Prediction & Speculation

5

Speculative Execution
ILP Optimizations

Intel P4
Power 5
Hyperthreading: Xeon

SATSIM Simulator

6

Exceptions



7

Caches

Moore’s Seminal Paper
The Memory Wall
The Memory Wall

Sample Problems: Memory Hierarchy

8

Memory



9

Coherency and Consistency

"Shared Memory Consistency Models: A Tutorial"
Coherence and Consistency Examples

Sample Problems: Coherence and Consistency

10

Instruction Scheduling



11

Register Allocation



12

Storage Systems



13

Interconnection Networks
Hypertransport
Commercial Examples


Janet: A Flit-Level Multiprocessor Network Simulator
Avici Terabit Router White Paper

14

Multi-core and Other Case Studies

Multicore Computing – Evolution
Multicore – Revisiting Parallelism
Guide to Multicore
Commercial Processors

Case Studies

*

Extra – PCI Express

PCI Express
HyperTransport


*Reference the Tomasulo Example in lecture notes for CS 252, Department of EECS, University of California, Berkeley, taught by Professor David Patterson and available at http://www.cs.berkeley.edu/~pattrsn/252S01/.