Q1: How many transistors are in the basic gates?
Q2: Can you determine transistor count from the gate icon?
Q3: Can I read simplified expressions from a mixed logic implementation?
Q4: In mixed logic, when do I consider the gate function versus its
I'm having trouble counting the number of transistor in the gate
designs that I have made.
NAND, NOR, NOT: transistors = 2 * # of inputs
AND, OR, transistors = 2 * # of inputs + 2
I thought I heard you say at one point that the reason that AND and OR
gates have 2i + 2 transistors is because of the inverters (accounting
for the extra 2). However, in doing these homework problems I have
just been counting everything as having 2i transistors and then
accounting 2 for every inverter in the gate design. Is it just a
coincidence that I get the same answers, or am I doing something wrong
(more than likely the case).
This is just a coincidence. Check the final gate type (regardless of
which deMorgan equivalent gate icon is drawn). Count each gate as
NAND, NOR, NOT: 2i
AND, OR: 2i+2
Then sum them up. Bubbled bars have no physical presence in the
design; so they contribute no transistors.
I am confused about the part where you are supposed to implement the
expression mixed logic methodology. I have double checked the reduced
expression, and each time I get -A*(-B+C). The answer shows this
correctly. However, if I am reading the mixed logic answer correctly,
it shows A+(B*-C). Have I made a mistake somewhere, or is the answer
When you are given an expression and asked to implement it using mixed
logic, in general, you won't simplify the expression. This would
defeat one of the benefits of mixed logic, namely that is documents
the implemented expression to illustrate the designer's intent. There
is no such feature of direct switch implementation; so you need to
change the expression in this case. If an expression is to be
simplified before it is implemented in gates, then the expression
captured in the mixed logic implementation is the simplified
The mixed logic expression reads -(A + B * -C) where "-" complements
the expression immediately following it.
I wanted to be sure I understand what you meant when you said "Check
the final gate type (regardless of which deMorgan equivalent gate icon
is drawn). " Does this mean that we just look at the overall body of
the gate? Like, if I had a NOR gate drawn as a standard AND gate with
the inputs complemented, then would that be 2i + 2 transistors (since
it's an AND body) or 2i transistors (since it's a NOR gate)?
Here's how one evaluates a mixed logic gate design. To determine the
behavior, ignore bubbles and consider gate bodies and bars. To
determine implementation cost, ignore bars and consider each
implemented gate type (including bubbles). In your question, the
answer is 2i because the implemented gate is a NOR gate.
questions and comments to Scott Wills