ECE3055 -  Computer Architecture and Operating Systems  (3-3-4)

Prerequisites:  ECE 2031

Corequisites:  None

Catalog Description:  Core concepts of computer architecture and operating systems. Instruction set architectures (ISA), compiler/ISA relationships, pipelined datapaths. Memory hierarchy, memory management, and protection. Processes, threads, CPU scheduling and associated techniques.

Textbook(s):  Silberschatz, Galvin, and Gagne, Operating System Concepts with Java (6th edition), John Wiley, 2004. ISBN 0471489050 (required) Patterson & Hennessey, Computer Organization & Design: The Hardware/Software Interface (3 edition), Morgan Kaufmann, 2004. ISBN 1-55860-604-1 (required) (comment: Will be using 2nd edition through Summer, 2004. 3rd edition available for Fall 2004)

Course Objectives - As part of this course, students: 1. build on ECE 2030 to enhance their understanding of core concepts of computer architecture related to processor, memory, and I/O subsystems. [6,8,11] 2. are introduced to core concepts of operating systems related to memory management, process and thread management, and I/O. [6] 3. will understand the interactions of hardware and software in a general-purpose computer system. [6,8,11] 4. gain laboratory-based experience in designing, implementing, and simulating hardware and software components of a computer system. [7,10,11] 5. utilize modern hardware and software design tools and languages in state-of-the-art facilities. [1,7,11]

Course Outcomes - Upon successful completion of this course, students should be able to: 1. evaluate cycles per instruction (CPI) for multi-cycle and pipelined data paths. 2. schedule machine-instruction-level programs on a pipelined datapath both with and without hazard handling. 3. define different types of data and control dependences and describe multiple methods of handling them. 4. design, using standard digital components, cache memories of different sizes and associativities. 5. describe several replacement policies for associative memory structures; e.g., set-associative caches or virtual memory pages. 6. determine the contents of a cache after execution of a memory trace. 7. define and understand virtual memory, including the concepts of paging, TLB, and page table. 8. determine the contents of a page table and TLB after execution of a memory trace. 9. describe I/O operation in a general-purpose computer system, including synchronous/asynchronous bus characteristics, bus arbitration schemes, and DMA. 10. define processes and threads. 11. construct and evaluate CPU schedules for a variety of scheduling algorithms. 12. define the problem of process/thread synchronization and describe several alternative mechanisms for handling synchronization. 13. define deadlock and describe several mechanisms for handling it. 14. step through an algorithm to determine if a given set of processes and resources are deadlocked.

Topical Outline:  Instruction Set Architectures (2 weeks) CISC and RISC: ISA evolution and tradeoffs Instruction formats, number of operands, addressing modes Controller implementation: state machine vs. microprogramming Effect of ISA on microarchitecture implementation Effect of ISA on the compiler Pipelining (4 weeks) Pipelining basics Pipeline stages: fetch, decode, execute, memory write-back Hazards and solutions Branch prediction and delayed branches Case Studies Memory Systems (3 weeks) Memory hierarchy Basic organization of caches, interleaved memory Virtual memory basics, memory management Deadlocks Segmentation and protection Case Studies Process Management (3 weeks) Processes, threads, and CPU scheduling Synchronization and concurrency management Deadlocks, protection, and security Case Studies I/O Architectures (2 weeks) Bus hierarchies, device drives Interrupts, DMA, polling Disk structures, I/O scheduling File allocation and file systems LANs, network interfaces, basic interprocessor communciation Case Studies Laboratory Assignments Architecture simulation Operating system project Grading Exam - 30% Quizzes (2) - 20% each Laboratory - 20% Homework - 10%