ECE3055 Fall'99 Homework Assignment #1
Due before 3:00 p.m. Tuesday 2/8/00
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#1. Consider the following instructions for a pipelined MIPS
processor with no data-forwarding or hazard-detection circuits:
add $s0, $t0, $t1
sub $t2, $s0, $t3
[ ] How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard)?
#2. Consider the following instructions for a pipelined MIPS
processor with no data-forwarding or hazard-detection circuits:
add $s0, $t0, $t1
add $s1, $t0, $t2
sub $t2, $s0, $t3
[ ] How many NOP's would have to be added between the first and
last instructions to prevent an error due the data dependency (or
hazard)?
[ ] Could the hazard be resolved by a different assembler technique
that would not slow down the program (Y for "yes", N for "no")?
#3. Consider the following instructions for a pipelined MIPS
processor:
lw $t0, 4($t1)
sw $t0, 4($t2)
[ ] How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard)
if the CPU did not have a data forwarding unit?
[ ] How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard)
if the CPU did have a data forwarding unit?
#4. Match up the following answers with the questions below.
A. Control hazard
B. Structural hazard
C. Data dependency
D. A stall or bubble
E. Dynamic branch prediction
F. Forwarding
[ ] Immediate use of data from a load word instruction.
[ ] Predicting a branch direction based on previous directions.
[ ] Immediate use of a register value that was just written.
[ ] Feeding back the output from the ALU to one of the ALU inputs.
[ ] Halting the IF and EX stages while letting other stages execute.
[ ] A branch instruction whose direction was not predicted.
#5. What will the operating system do:
A. Save the state of the process so it can be restarted later.
B. Halt execution and send an error message to the user.
in a pipelined machine when the following events occur:
[ ] An ALU overflow.
[ ] An I/O interrupt.
[ ] An illegal instruction.
[ ] An illegal memory address.
[ ] An operating system service call.
#6. In what stage do the following appear in the MIPS architecture?
Answers: IF, ID, EX, MEM, WB
[ ] Forwarding Unit
[ ] Hazard detection unit
[ ] Data memory
[ ] Program memory
[ ] (CPU) Control
[ ] Register writing from memory or ALU result
[ ] Register writing of immediate data
[ ] ALU
[ ] Branch direction unit (=)
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